Marvell International Limited

Yicheng Guo

Hunglin Hsu

Viney Gautam

Warren Menezes

An apparatus comprises an event memory to store one or more events, and a prefetch circuit. The prefetch circuit a) detects a current stride between a first address and a second address, b) detects a stride break using the current stride and a stride of a first dimension, and c) stores a first event in the event memory when the stride break is detected. The first event includes i) an event address corresponding to the first address, and ii) a stride corresponding to the current stride. A method for generating a prefetch address comprises detecting, by a prefetch circuit, a first stride break between a first address of a stream and a second address of the stream, storing, in the prefetch circuit, a first event corresponding to the first stride break; and generating, by the prefetch circuit, an output prefetch address using the stored first event.

Multi-dimensional prefetching

A circuit has an address generation circuit to produce a virtual address (VA) and an index signal and a multi-way cache circuit. The cache circuit has a plurality of Random Access Memory (RAM) groups and a hash function circuit to generate a hash output from the VA. Each RAM group includes RAMs respectively corresponding to the ways. The cache circuit selects, using the hash output, a selected RAM group of the RAM groups, and performs, using the index signal as an address, an operation using one or more RAMs of the selected RAM group. Controlling a multi-way cache circuit comprises determining a hash value using a VA, selecting, using the hash value, a RAM group from a plurality of RAM groups, and performing an operation by using one or more RAMs of the selected RAM group. The RAMs of each RAM group respectively correspond to the ways.

Data caching circuit and method

In aspects of determining memory access patterns for cache prefetch in an out-of-order processor, data is maintained in a cache when copied from system memory of a computing device, and load data instructions are processed to access the cache data. The load data instructions include incremental load data instructions and non-incremental load data instructions that access the data from contiguous memory addresses. The data is prefetched ahead of processing the load data instructions, where prefetch requests are initiated based on the load data instructions. A stride is calculated as the distance between the incremental load data instructions. Further, the stride can be corrected for the non-incremental load data instructions to correlate with the calculated stride. The corrected stride represents the data as a sequential data stream having a fixed stride, and prefetching the data appears sequential for both the incremental and non-incremental load data instructions.

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Milpitas, CA, United States of America

Yicheng Guo