Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Yichen Wang

Liang Li

Ming Wang

Wei Zhang

Jiahui Yuan

Ming Hsi Wang

Anubhav Khandelwal

Will Li

Bruce Li

To improve memory cell endurance and erase times for non-volatile memories, such as NAND memory, a sub-block based adaptive erase pulse is used. In a memory structure where the array is composed of blocks that have multiple sub-blocks, after applying an erase pulse to an erase selected block, one of the sub-blocks is erased verified and, if it fails to verify, the next erase pulse's duration is tuned based on the number of memory cells of that sub-block that fail to verify. If the first verified one of the sub-blocks verifies, the other sub-blocks of the erase selected block are erased verified, with the next erase pulse's duration tuned based on the number of the other sub-blocks that fail to verify.

Adaptive erase pulse to improve memory cell endurance and erase time in non-volatile memory

An apparatus includes a memory structure including non-volatile memory cells, and a control circuit coupled to the memory cell. The control circuit configured to first read a block of non-volatile memory cells using a first plurality of read levels, determine that the first read fails to successfully read the block of non-volatile memory cells, second read the block of memory cells using a second plurality of read levels different from the first plurality of read levels, determine that the second read successfully reads the block of non-volatile memory cells, estimate that the first read failed because of data retention or read disturb, and erase and re-write data to the block of non-volatile memory cells.

Apparatus and methods for read retry with conditional data refresh

Embodiments disclosed herein are directed to a memory device, comprising control circuitry configured to: perform a broad voltage level range bit error rate estimation scan to identify an approximate optimal read reference voltage for a first string; perform a narrow voltage level range bit error rate estimation scan, using the approximate optimal read reference voltage, to determine an optimal read reference voltage for the first string; and perform the narrow voltage level range bit error rate estimation scan, using the approximate optimal read reference voltage, to determine an optimal read reference voltage for a second string, wherein the broad voltage level range bit error rate estimation scan includes scanning a broader range of voltage levels than the narrow voltage level range bit error rate estimation scan.

Enhanced bit error rate estimation scan process

Apparatuses and techniques are described for programming memory cells with a reduced number of program pulses. A program operation includes a first, foggy program pass followed by a second, fine program pass. The number of program loops in the foggy program pass is minimized while providing relatively narrow Vth distributions for the foggy states. The program loops include one or more checkpoint program loops in which a program speed of the memory cells is determined through a read operation. In a next program loop, the fast-programming memory cells are inhibited from programming while the slow-programming memory cells are programmed with a reduced speed by applying a program speed-reducing bit line voltage. This brings the threshold voltage of the slow-programming memory cells into alignment with the threshold voltage of the fast-programming memory cells.

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Shanghai, China

Yichen Wang