Lightelligence Pte. Ltd.

Massachusetts Institute of Technology

Lux Labs, Inc.

Hangzhou Guangzhiyuan Technology Co., Ltd.

Yichen Shen

Huaiyu Meng

Marin Soljacic

Cheng-Kuan Lu

Maurice B Steinman

Li Jing

Ronald Gagnon

Jianhua Wu

Arash Hosseinzadeh

Rumen Rumenov Dangovski

Matthew Raja Khoury

Scott A Skirlo

Dirk Robert Englund

Nicholas Christopher Harris

JingDong Deng

Peng Xie

Mihika Prabhu

Jacques Johannes Carolan

Yelong Xu

Longwu Ou

Gilbert Hendry

Jonathan Terry

John Dimitris Joannopoulos

Charles Roques-Carmes

Yanfei Bai

Tena Dubcek

Hengameh Bagherianlemraski

Steven G Johnson

Evelyn N Wang

Zhan Su

Ivan Celanovic

Bikramjit S Bhatia

Ido Kaminer

Ognjen Ilic

Liang Jie Wong

Mike Evans

Dexin Ye

Wei Li

Kezhen Yin

Samuel Jiang

Shanshan Yu

Hui Chen

Arny Leroy

A method for assembling a photonic computing system includes attaching a photonic source to a support structure, and attaching a photonic integrated circuit to the support structure. The photonic source includes a first laser die on a substrate configured to provide a first optical beam, and a second laser die on the substrate configured to provide a second optical beam. The photonic integrated circuit includes a first waveguide and a first coupler coupled to the first waveguide, and a second waveguide and a second coupler coupled to the second waveguide. The method includes attaching a plurality of beam-shaping optical elements to the support structure, the substrate, or the photonic integrated circuit, in which the attaching includes aligning a first beam-shaping optical element during attachment so that the first optical beam is coupled to the first coupler, and aligning a second beam-shaping optical element during attachment so that the second optical beam is coupled to the second coupler.

Photonic computing platform

A photonic parallel network can be used to sample combinatorially hard distributions of Ising problems. The photonic parallel network, also called a photonic processor, finds the ground state of a general Ising problem and can probe critical behaviors of universality classes and their critical exponents. In addition to the attractive features of photonic networks—passivity, parallelization, high-speed and low-power—the photonic processor exploits dynamic noise that occurs during the detection process to find ground states more efficiently.

Optical Ising machines and optical convolutional neural networks

A radiative cooling device can include a reflector positionable to permit operation during daylight hours.

Passive radiative cooling during the day

An optical neural network is constructed based on photonic integrated circuits to perform neuromorphic computing. In the optical neural network, matrix multiplication is implemented using one or more optical interference units, which can apply an arbitrary weighting matrix multiplication to an array of input optical signals. Nonlinear activation is realized by an optical nonlinearity unit, which can be based on nonlinear optical effects, such as saturable absorption. These calculations are implemented optically, thereby resulting in high calculation speeds and low power consumption in the optical neural network.

Apparatus and methods for optical neural network

A system includes a first unit configured to generate a plurality of modulator control signals, and a processor unit. The processor unit includes: a light source or port configured to provide a plurality of light outputs, and a first set of optical modulators coupled to the light source or port and the first unit. The optical modulators in the first set are configured to generate an optical input vector by modulating the plurality of light outputs provided by the light source or port based on digital input values corresponding to a first set of modulator control signals in the plurality of modulator control signals, the optical input vector comprising a plurality of optical signals. The processor unit also includes a matrix multiplication unit that includes a second set of optical modulators. The matrix multiplication unit is coupled to the first unit, and is configured to transform the optical input vector into an analog output vector based on a plurality of digital weight values corresponding to a second set of modulator control signals in the plurality of modulator control signals applied to the second set of optical modulators. At least one optical modulator of at least one of the first set of optical modulators or the second set of optical modulators is configured to modulate an optical signal based on a first modulator control signal among the plurality of modulator control signals, and the first unit is configured to shape the first modulator control signal to include bandwidth-enhancement associated with a change in amplitude associated with a corresponding change in successive digital values corresponding to the first modulator control signal.

Optoelectronic computing systems

The present disclosure provides a three-dimensional packaging method and a three-dimensional package structure of a photonic-electronic chip. The method includes: fixing an electronic chip on a first area of a first surface of a photonic chip; fixing a dummy chip on a second area of the first surface of the photonic chip, wherein the photonic chip is provided with an optical coupling interface at the second area, and the dummy chip has a cavity with a single-sided opening, and the opening of the cavity faces and covers an optical coupling interface.

Three-dimentional packaging method and package structure of photonic-electronic chip

Systems and methods that include: providing input information in an electronic format; converting at least a part of the electronic input information into an optical input vector; optically transforming the optical input vector into an optical output vector based on an optical matrix multiplication; converting the optical output vector into an electronic format; and electronically applying a non-linear transformation to the electronically converted optical output vector to provide output information in an electronic format. In some examples, a set of multiple input values are encoded on respective optical signals carried by optical waveguides. For each of at least two subsets of one or more optical signals, a corresponding set of one or more copying modules splits the subset of one or more optical signals into two or more copies of the optical signals. For each of at least two copies of a first subset of one or more optical signals, a corresponding multiplication module multiplies the one or more optical signals of the first subset by one or more matrix element values using optical amplitude modulation. For results of two or more of the multiplication modules, a summation module produces an electrical signal that represents a sum of the results of the two or more of the multiplication modules.

An optoelectronic computing system includes a first semiconductor die having a photonic integrated circuit (PIC) and a second semiconductor die having an electronic integrated circuit (EIC). The PIC includes optical waveguides, in which input values are encoded on respective optical signals carried by the optical waveguides. The PIC includes an optical copying distribution network having optical splitters. The PIC includes an array of optoelectronic circuitry sections, each receiving an optical wave from one of the output ports of the optical copying distribution network, and each optoelectronic circuitry section includes: at least one photodetector detecting at least one optical wave from the optoelectronic operation. The EIC includes electrical input ports receiving respective electrical values. The first semiconductor die and the second semiconductor die are electrically coupled in a controlled collapse chip connection, with the electrical output port of the PIC connected to one of the electrical input ports of the EIC.

An apparatus having a segmented optical modulator includes an optical waveguide having three or more segments. Each of three or more optical modulators includes a corresponding waveguide segment and is configured to apply an optical modulation that is proportional to the length of the segment. Three or more electrical contacts receive respective bit values of binary values. Each binary value includes at least three bit values including a least significant bit (LSB) bit value, a most significant bit (MSB) bit value, and at least one intermediate bit (IB) bit value between the LSB bit value and the MSB bit value. At least one waveguide segment of a corresponding optical modulator receiving an LSB bit value is positioned between a first waveguide segment of a corresponding optical modulator receiving an MSB bit value and a second waveguide segment of a corresponding optical modulator receiving an IB bit value.

Optical modulation for optoelectronic processing

An integrated circuit interposer includes a semiconductor substrate layer; a first metal contact layer including a first metal contact section that includes metal contacts arranged for electrically coupling to a first semiconductor die in a controlled collapsed chip connection, and a second metal contact section that includes metal contacts arranged for electrically coupling to a second semiconductor die in a controlled collapsed chip connection. A first patterned layer includes individually photomask patterned metal path sections. A second patterned layer includes individually photomask patterned waveguide sections, including a first waveguide that crosses at least one boundary between individually photomask patterned waveguide sections. A first modulator is coupled to the first waveguide for modulating an optical wave in the first waveguide based on an electrical signal received at a first metal contact in the first metal contact section, and a second modulator is coupled to the first waveguide for modulating the optical wave based on an electrical signal received at a second metal contact in the first metal contact section or the second metal contact section.

Optoelectronic computing platform

Data to be processed includes vector element values of an input vector and matrix element values of a model matrix associated with a neural network model. A vector-matrix multiplication module receives a set of matrix element values for performing a vector-matrix multiplication operation. Processing the data includes computing a plurality of intermediate vectors based on element-wise vector multiplication between different subsets of the vector element values and different respective pre-processing vectors. The vector-matrix multiplication module is loaded with a core matrix, and the input vector is multiplied by the model matrix based on separately multiplying each of the intermediate vectors by the loaded core matrix.

Processing matrix operations for rate limited systems

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Cambridge, MA, United States of America

Yichen Shen