Qualcomm Incorporated

Montage Technology (kunshan) Co., Ltd.

Montage Technology Co., Ltd.

Other

Montage Technology Group Limited

Montage Technology Inc.

Yibo Jiang

Sharad Deepak Sambhwani

Jilei Hou

Leechung Yiu

Lizhi Jin

Lei Xu

Xiaohui Liu

Yanming Zou

Jiangtao Ren

Robert Xi Jin

Gang Shan

Christopher Cox

Larry Wu

Gang Yan

Wei Zeng

Haitong Sun

Mehmet Yavuz

Aziz Gholmieh

Jibing Wang

Arjun Bharadwaj

Danlu Zhang

Bibhu P Mohanty

Pavan Kumar Vitthaladevuni

Jason Frank Hunzinger

Lu Yuan

Leonard Datus

Bibhu Prasad Mohanty

A clock driver comprises: an input multiplexer for receiving a plurality pairs of input clock signals and an input selection signal, and for selectively outputting one pair of the plurality pairs of input clock signals according to the input selection signal; a phase locking loop (PLL) coupled to the input multiplexer to receive one pair of the plurality pairs of input clock signals, and for generating a PLL clock signal according to the received pair of input clock signals; at least two sets of output multiplexers coupled to the PLL to receive the PLL clock signal and an output selection signal, wherein each set of output multiplexers are configured to selectively output the PLL clock signal as a set of output clock signals according to the output selection signal to drive at least one group of memory chips; and a control module configured to detect toggling of the plurality pairs of input clock signals and generate the input selection signal and the output selection signal based on a detection result of the toggling of the plurality pairs of input clock signals.

Clock driver and memory device comprising the same

An apparatus for controlling access to a memory device comprising rows of memory units is provided. The apparatus comprises: an operation monitor configured to track memory operations to the rows of memory units of the memory device; a row hammer counter configured to determining, for each of the rows of memory units, row hammer effects experienced by the row of memory units due to the memory operations to the other rows of memory units of the memory device; a mitigation module configured to initiate, for each of the rows of memory units, row hammer mitigation in case that accumulated row hammer effects experienced by the row of memory units reach a predetermined threshold; and a virtual host module configured to perform the row hammer mitigation targeting a row of memory units in response to the initiation of row hammer mitigation for the row of memory units by the mitigation module.

Apparatus for controlling access to a memory device and memory system comprising the same

Various embodiments include methods for improving navigation by a processor of a robotic device. Such embodiments may include initiating a start of a predetermined time period associated with semantic information extraction, and determining whether an adverse event related to one or more sensors of the robotic device is detected. Such embodiments may also include identifying a current time slot of the predetermined time period, identifying a current estimated position and orientation of the robotic device, and recording updates to semantic information stored for the one or more sensor based on the identified current time slot and the current estimated position and orientation of the robotic device in response to determining that an adverse event related to one or more sensors of the robotic device is detected.

Systems and methods for utilizing semantic information for navigation of a robotic device

A clock driver comprises: a clock detector for receiving a plurality pairs of input clock signals of a predetermined clocking protocol, and for generating a protocol identifier indicative of the predetermined clocking protocol; a phase locking loop (PLL) module coupled to receive at least one pair of the plurality pairs of input clock signals, and for generating at least one pair of reference clock signals according to the received at least one pair of input clock signal; and a plurality of multiplexers coupled to the clock detector and to the PLL module. Each multiplexer is configured for receiving one pair of the plurality pairs of input clock signals and one pair of the at least one pair of reference clock signals, and selectively outputting, according to the protocol identifier, the pair of input clock signals and the pair of reference clock signals to drive a group of memory chips.

Various embodiments include processing devices and methods for relocation and reinitialization for a robotic device. Various embodiments may include concurrently relocating a second pose of the robotic device and reinitializing a third pose of the robotic device in response to failing to determine a first pose of the robotic device in the environment and determining that tracking of the robotic device is lost. Various embodiments may include pre-relocating a second pose of the robotic device in the environment in response to failing to determine the first pose of the robotic device in the environment and determining that tracking of the robotic device is lost, relocating a third pose of the robotic device in response to successfully pre-relocating the second pose of the robotic device, and reinitializing a fourth pose of the robotic device in response to unsuccessfully pre-relocating the second pose of the robotic device.

Concurrent relocation and reinitialization of VSLAM

Various embodiments include processing devices and methods for initializing an image sensor of a robotic vehicle. In some embodiments, a processor of the robotic vehicle may extract first features from a captured image of the target image, may extract second features from a predefined image pyramid of the target image, may match first features and second features, and may estimate an image sensor pose based on matched features and known dimensions of the target image. In some embodiments, the processor may estimate an image or to image sensor pose based on matched features and a translation and/or rotation of the robotic vehicle. In some embodiments, the processor may determine a coordinate system for the robotic vehicle based on one or more image sensor poses.

Image sensor initialization in a robotic vehicle

A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers, later than the target access CS signal, a command and address (CA) signal for addressing and accessing the multiple memory cells of the target memory rank; and wherein the target local controller is configured to generate, in response to receiving the target access CS signal, a target CA on-die termination (ODT) instruction switching on target CA ODT at its CA input at least for a period when the CA signal is being received from the memory controller.

On-die termination control for memory systems

A memory system, comprising: a first plurality of memory ranks each having multiple memory cells; a second plurality of local controllers each coupled between one or more of the first plurality of memory ranks and a memory controller, the memory controller being configured to provide to a non-target local controller of the second plurality of local controllers, out of a first plurality of chip select (CS) signals, one or more non-target access CS signals disabling target access to one or more non-target memory ranks of the first plurality of memory ranks coupled to the non-target local controller; and the memory controller being further configured to provide to a target local controller of the second plurality of local controllers, out of the first plurality of CS signals, a target access CS signal enabling target access to a target memory rank of the first plurality of memory ranks coupled to the target local controller, and provide to the second plurality of local controllers a command and address (CA) signal for addressing and accessing the multiple memory cells of the target memory rank; and wherein the non-target local controller is configured to provide to the non-target memory ranks, in response to receiving the one or more non-target access CS signals, one or more composite on-die termination (ODT) instructions which instruct respective ones of the one or more non-target memory ranks to selectively switch on non-target DQ/DQS ODT for a data communication bus coupled between the first plurality of memory ranks and the memory controller at least for a period when the memory controller is performing target access to the target memory rank; wherein each composite ODT instruction comprises a combination of secondary CS instruction(s) and a secondary CA instruction.

Memory system and method for accessing memory system

A base station receiver, a computer program product operable at a base station, and a method operable at a base station receiver, for receiving uplink transmit diversity transmissions utilizing a master/slave scheme at the receiver. One or more tracking loops, such as a searcher task, a time tracking loop, or a frequency tracking loop may be implemented at the base station receiver to determine compensation values, such as finger timings for a rake receiver or frequency compensation values, in accordance with characteristics of a first received pilot channel transmitted utilizing a first precoding weight vector. Here, corresponding compensation values may be derived for the reception of a secondary pilot channel transmitted utilizing an precoding weight vector orthogonal to the first precoding weight vector, simply based on those determined for the first pilot channel.

Master-slave architecture in a closed loop transmit diversity scheme

An apparatus, method, and computer program product operable to determine a phase of a beamforming weight vector utilizing a memory of a previously used phase for the beamforming weight vector, capable of improving a channel estimate. A base station transmits a beamforming weight vector to a user equipment based on a determined channel estimate. The user equipment selects between the received beamforming weight vector, or a modified beamforming weight vector having its phase shifted by &#x2212;360&#xb0;, in accordance with a suitable selection criteria. That is, the selection is made such that a difference between the phase of the selected beamforming vector and a phase of a prior beamforming vector is within a predetermined range.

Apparatus and method for uplink closed loop transmit diversity

A method and apparatus for enabling uplink beamforming transmit diversity is provided. The method may include receiving, by a wireless communications device (WCD), a beamforming weight vector in response to transmission by the WCD of two or more pilot channels, applying the received beamforming weight vector to at least one of a first of the two or more pilot channels, one or more data channels, or one or more control channels, and transmitting, using two or more antennas, at least one of the one or more data channels or at least one of the one or more control channels, wherein the number of pilot channels is greater than or equal to the number of antennas.

Apparatus and method for enabling uplink beamforming transit diversity

Apparatus and methods for communicating in a wireless network include receiving a weight vector in a slot for providing closed loop transmit diversity to signals in a next slot, holding the weight vector over a plurality of slots following a transmission burst, and applying the weight vector to signals in at least one slot of a subsequent transmission burst in discontinuous transmit. Additional apparatus and methods for communicating in a wireless network include determining a weight vector based on signals received from a device to provide closed loop transmit diversity feedback to the device, holding the weight vector over a plurality of slots following receiving a transmission burst, and applying the weight vector for signals received in at least one slot of a subsequent transmission burst from the device.

Closed loop transmit diversity in continuous packet connectivity

A method for closed loop transmit diversity that includes receiving data from user equipment (UE) that was transmitted using multiple transmit antennas, selecting a new transmit antenna for the UE, determining a new cycle period for the UE, and sending a new transmit antenna index and a testing indication based on the new cycle period to the UE.

Antenna switching in a closed loop transmit diversity system

A Registered DIMM (RDIMM) system with reduced electrical loading on the data bus for increases memory capacity and operation frequency. In one embodiment, the data bus is buffered on the DIMM. In another embodiment, the data bus is selectively coupled to a group of memory chips via switches.

Registered DIMM memory system

A method and apparatus for enabling uplink beamforming transmit diversity channel estimation is provided. The method may include receiving a primary pilot channel and a secondary pilot channel, deriving two or more composite channels from the received primary and secondary pilot channels, deriving two or more physical channels from the derived two or more composite channels, and synthesizing a composite channel estimate for a dominant virtual antenna from the two or more derived physical channels and a beamforming weight vector.

Growing community of inventors

San Diego, CA, United States of America

Yibo Jiang