Intel Corporation

Pacific Rim International, LLC

Yibin Ye

Vivek K De

Dinesh Somasekhar

Muhammad M Khellah

Stephen H Tang

Ali Keshavarzi

Fabrice Paillet

Shih-Lien L Lu

James W Tschanz

Siva G Narendra

Nam Sung Kim

Fatih Hamzaoglu

Mohsen Alavi

Tanay Karnik

Gerhard Schrom

Kevin X Zhang

Brian S Doyle

Suman Datta

Gunjan H Pandya

Bo Zheng

Jianping Xu

Zhanping Chen

Liqiong Wei

Mircea R Stan

David M Wu

Maged Ghoneima

Ali R Farhang

Reed D Spotten

Georgios Stamoulis

Khellah Muhammad

Muhammad Kheliah

Alavi Mohsen

Hyungwon Kim

A trailer coupler may be provided with an opening and socket for a hitch ball, and a clamping bar in an internal channel for locking the coupler and hitch together. The internal channel may extend horizontally and be positioned above the opening and below the socket. The channel may include a laterally-facing aperture adjacent the second end, out of which one end of the clamping bar may extend. That end of the clamping bar may include a bracket with an open channel to fit over a flange on the coupler body. The coupler may be assembled by inserting a first end of the clamping bar through the laterally-facing aperture, and moving the first end of the clamping bar into the coupler body channel while fitting the bracket over the flange at the open channel of the clamping bar.

Trailer coupler

Described herein is an apparatus for adjusting a power supply level for a memory cell to improve stability of a memory unit. The apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error.

Memory cell supply voltage control based on error detection

In some embodiments, provided is an integrated circuit with a first die coupled to a second die. The second die has through-silicon vias disposed through it to provide power references to the first die. The through-silicon vias are laterally re-positionable without inhibiting circuit sections in the second die.

Multi-die integrated circuit device and method

For one embodiment, an apparatus comprises memory circuitry including memory cells, error detection circuitry to detect error in data stored by memory cells of the memory circuitry, and supply voltage control circuitry to increase supply voltage for one or more memory cells of the memory circuitry based at least in part on detected error. Other embodiments have one or more other features.

A method and apparatus for bus repeater tapering. The sizing of repeaters on a portion of one transmission line is chosen to propagate a signal transition at a particular rate. The sizing of repeaters on a substantially parallel portion of another transmission line, is chosen to propagate a second signal transition at a different rate. Thus, the worst-case capacitance coupling factor between the two transmission lines may be reduced.

Method and apparatus for bus repeater tapering

For one embodiment, an apparatus may include a memory cell to store a bit value, wherein the memory cell may lose the bit value in response to a memory access operation. The apparatus may also include first circuitry to detect whether the memory cell loses the bit value in response to the memory access operation and second circuitry to restore the bit value in the memory cell in response to detection that the memory cell loses the bit value. Other embodiments include other apparatuses, methods, and systems.

Memory cell bit valve loss detection and restoration

For one disclosed embodiment, an integrated circuit may comprise a memory array on the integrated circuit and access control circuitry on the integrated circuit. The memory array may have a bit line with one or more resistors along the bit line and may have a plurality of memory cells coupled to the bit line at a plurality of locations along the bit line. At least one resistor along the bit line may be between two locations at which memory cells are coupled to the bit line. The access control circuitry may be to select a memory cell coupled to the bit line and to sense a signal on the bit line from the selected memory cell. Other embodiments are also disclosed.

Memory having bit line with resistor(s) between memory cells

A memory system having a selectable configuration for sense amplifiers is included. The memory system can include bit cells and a switch module coupled to the bit cell and to a first portion of a sense amplifier. The switch module can connect, disconnect or cross couple the bit cell to the sense amplifier based on a test for the input offset voltage of first portion of the sense amplifier. A similar configuration can be implemented by a second portion of the sense amplifier. The system can also include a programmer module to configure a setting of the switch module and can include a column select module to couple the bit cells to the sense amplifiers based on what column of bit cell is to be read. Other embodiments are also disclosed.

Sense amplifier method and arrangement

A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

Floating-body dynamic random access memory and method of fabrication in tri-gate technology

Some embodiments provide a memory cell that includes a body region, a source region and a drain region. The body region is doped with charge carriers of a first type, the source region is disposed in the body region and doped with charge carriers of a second type, and the drain region is disposed in the body region and doped with charge carriers of the second type. The body region and the source region form a first junction, the body region and the drain region form a second junction, and a conductivity of the first junction from the body region to the source region in a case that the first junction is unbiased is substantially less than a conductivity of the second junction from the body region to the drain region in a case that the second junction is unbiased.

Asymmetric memory cell

A SRAM device is provided having a plurality of memory cells. Each memory cell may include a plurality of transistors coupled in a cross-coupled inverter configuration. An NMOS transistor may be coupled to a body of the two PMOS transistors in the cross-coupled inverter configuration so as to apply a forward body bias to the PMOS transistors of the cross-coupled inverter configuration. A power control unit may control a supply voltage to each of the PMOS transistors as well as apply the switching signal to the NMOS transistor based on a STANDBY mode of the memory cell.

SRAM device having forward body bias control

In some embodiments, a memory array is provided with cells that when written to or read from, can have modified supplies to enhance their read stability and/or write margin performance. Other embodiments may be disclosed and/or claimed.

Growing community of inventors

Portland, OR, United States of America

Yibin Ye