Yangtze Memory Technologies Co., Ltd.

Yi Zhou

Wei Zhang

Jun Zhang

Sicong Wang

Xiaoye Ding

Yuanxiang Zou

Le Wang

Li Zhang

Xinsheng Wang

Gaosheng Zhang

Xiongyu Wang

Hsing-An Lo

YuPing Xia

Fei Xie

In a method for fabricating a semiconductor device, a stack of alternating insulating layers and sacrificial layers are formed over a substrate. A staircase having a plurality of steps are formed in the stack. Each of the steps has a tread and a riser and further includes a respective pair of the insulating layer and the sacrificial layer over the insulating layer of the respective step. A dielectric layer is formed along the treads and risers of the steps and is doped with one or a combination of carbon, phosphorous, boron, arsenic, and oxygen. The sacrificial layers are further replaced with a conductive material to form word line layers that are arranged between the insulating layers. A plurality of word line contacts are formed to extend from the word line layers of the plurality of steps, and further extend through the dielectric layer.

Structures and methods for fabricating staircase regions of a three-dimensional NAND memory device

Embodiments of systems and methods for measuring a surface topography of a semiconductor structure are disclosed. In certain examples, a plurality of interference signals, each corresponding to a respective one of a plurality of positions on a surface of the semiconductor structure, are measured. Calibration signals, associated with a baseline region corresponding to a first category of a plurality of categories and a calibrated region corresponding to a second category of the plurality of categories, are measured. A surface height offset, associated with the baseline region and the calibrated region, is determined based on original surface heights and the calibration signals. The original surface heights are determined based on the plurality of interference signals corresponding to the baseline region and the calibrated region. The surface topography of the semiconductor structure is characterized based, at least in part, on the surface height offset and the original surface heights.

Systems and methods for semiconductor chip surface topography metrology

In certain aspects, a method for training a model is disclosed. A model for measuring a geometric attribute of a hole structure in a semiconductor chip is provided by at least one processor. A plurality of training samples each including a pair of an optical spectrum signal and a reference signal corresponding to a same hole structure are obtained by the at least one processor. The reference signal is labeled with a labeled geometric attribute of the hole structure. An estimated geometric attribute of the hole structure is estimated using the model. A parameter of the model is adjusted based, at least in part, on a difference between the labeled geometric attribute and the estimated geometric attribute in each of the training samples by the at least one processor.

Systems and methods for semiconductor chip hole geometry metrology

Embodiments of systems and methods for measuring a surface topography of a semiconductor chip are disclosed. In an example, a method for measuring a surface topography of a semiconductor chip is disclosed. A plurality of interference signals each corresponding to a respective one of a plurality of positions on a surface of the semiconductor chip are received by at least one processor. The plurality of interference signals are transformed by the at least one processor into a plurality of spectrum signals each corresponding to the respective one of the positions on the surface of the semiconductor chip. The spectrum signals are classified by the at least one processor into a plurality of categories using a model. Each of the categories corresponds to a region having a same material on the surface of the semiconductor chip. A surface height offset between a surface baseline and at least one of the categories is determined by the at least one processor based, at least in part, on a calibration signal associated with the region corresponding to the at least one of the categories. The surface topography of the semiconductor chip is characterized by the at least one processor based, at least in part, on the surface height offset and the interference signals.

Embodiments of systems and methods for measuring a geometric attribute of a hole structure in a semiconductor chip are disclosed. In an example, an optical spectrum signal corresponding to the hole structure in the semiconductor chip is received. The optical spectrum signal is characterized by one or more optical features. The geometric attribute of the hole structure is determined based, at least in part, on the optical features using a model. The model is trained from a plurality of training samples each including a pair of an optical spectrum signal and a labeled reference signal both corresponding to a same hole structure.

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Wuhan, China

Yi Zhou