Taiwan Semiconductor Manufacturing Comp. Ltd.

Yi-Yun Li

Huicheng Chang

Yee-Chia Yeo

Tsai-Yu Huang

Li-Ting Wang

Xiong-Fei Yu

Che-Hao Chang

Cheng-Po Chau

Hung-Yao Chen

Terry Huang

A semiconductor device and a method of forming the same are provided. A method includes forming a fin structure on a substrate. The fin structure includes a plurality of first nanostructures and a plurality of second nanostructures alternately stacked. A dummy gate is formed along sidewalls and a top surface of the fin structure. A portion of the fin structure exposed by the dummy gate is recessed to form a first recess. An epitaxial source/drain region is formed in the first recess. Dopant atoms within the epitaxial source/drain region are driven into the plurality of second nanostructures. The dummy gate and the plurality of first nanostructures are removed. A replacement gate is formed wrapping around the plurality of second nanostructures.

Nanostructure FET and method of forming same

A method for forming a semiconductor structure is provided. The method includes forming a fin structure over a substrate and forming an isolation structure over the substrate. In addition, the fin structure is protruded from the isolation structure. The method further includes trimming the fin structure to a first width and forming a Ge-containing material covering the fin structure. The method further includes annealing the fin structure and the Ge-containing material to form a modified fin structure. The method also includes trimming the modified fin structure to a second width.

Semiconductor structure and method for forming the same

Embodiments described in this disclosure relate to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In some examples, after an interfacial layer and a gate dielectric layer are deposited, a rapid anneal process, such as laser anneal or flash lamp anneal process, is performed in a controlled ambient nitrogen-containing environment to form a nitrided portion in the gate dielectric layer. The nitrided portion passivates the defects at the surface of the gate dielectric layer and can serve as a barrier to prevent etchant chemistry and defects/dopants from the subsequent gate stack layers from affecting or diffusing through the gate dielectric layer. Particularly, the rapid anneal process is performed on a millisecond scale to confine nitrogen atoms in the gate dielectric layer without diffusing into the underlying interfacial dielectric and/or any neighboring structure such as fin.

Thermal treatment for gate dielectrics

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Hsinchu, Taiwan

Yi-Yun Li