Taiwan Semiconductor Manufacturing Comp. Ltd.

Yi Yang Wei

Hsun-Chung Kuang

Bi-Shen Lee

Hai-Dang Trinh

Cheng-Yuan Tsai

Hsing-Lien Lin

Fa-Shen Jiang

Tzu-Yu Lin

Hsin-Yu Lai

A method includes forming a bottom electrode layer, and depositing a first ferroelectric layer over the bottom electrode layer. The first ferroelectric layer is amorphous. A second ferroelectric layer is deposited over the first ferroelectric layer, and the second ferroelectric layer has a polycrystalline structure. The method further includes depositing a third ferroelectric layer over the second ferroelectric layer, with the third ferroelectric layer being amorphous, depositing a top electrode layer over the third ferroelectric layer, and patterning the top electrode layer, the third ferroelectric layer, the second ferroelectric layer, the first ferroelectric layer, and the bottom electrode layer to form a Ferroelectric Random Access Memory cell.

FeRAM with laminated ferroelectric film and method forming same

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a lower electrode structure disposed over one or more interconnects. The one or more interconnects are arranged within a lower inter-level dielectric (ILD) structure over a substrate. A barrier is arranged along a lower surface of the lower electrode structure. The barrier separates the lower electrode structure from the one or more interconnects. An amorphous initiation layer is over the lower electrode layer and a ferroelectric material is on the amorphous initiation layer. The ferroelectric material has a substantially uniform orthorhombic crystalline phase. An upper electrode is over the ferroelectric material.

Interface film to mitigate size effect of memory device

Ferroelectric stacks are disclosed herein that can improve retention performance of ferroelectric memory devices. An exemplary ferroelectric stack has a ferroelectric switching layer (FSL) stack disposed between a first electrode and a second electrode. The ferroelectric stack includes a barrier layer disposed between a first FSL and a second FSL, where a first crystalline condition of the barrier layer is different than a second crystalline condition of the first FSL and/or the second FSL. In some embodiments, the first crystalline condition is an amorphous phase, and the second crystalline condition is an orthorhombic phase. In some embodiments, the first FSL and/or the second FSL include a first metal oxide, and the barrier layer includes a second metal oxide. The ferroelectric stack can be a ferroelectric capacitor, a portion of a transistor, and/or connected to a transistor in a ferroelectric memory device to provide data storage in a non-volatile manner.

Ferroelectric memory device and method of manufacturing the same

In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect dielectric layers arranged over a substrate. A bottom electrode is disposed over a conductive structure and extends through the one or more interconnect dielectric layers. A top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts the bottom electrode and the top electrode. The ferroelectric layer includes a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion coupling the first lower horizontal portion to the first upper horizontal portion.

Memory window of MFM MOSFET for small cell size

In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a bottom electrode layer over a substrate and forming a seed layer over the bottom electrode layer. A ferroelectric switching layer is formed over the bottom electrode layer and to contact the seed layer. The ferroelectric switching layer is formed to have a first region with a first crystal phase and a second region with a different crystal phase. A top electrode layer is formed over the ferroelectric switching layer. One or more patterning processes are performed on the bottom electrode layer, the seed layer, the ferroelectric switching layer, and the top electrode layer to form a ferroelectric random access memory (FeRAM) device.

Ferroelectric random access memory device with seed layer

In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes forming a lower electrode layer over a substrate, and an un-patterned amorphous initiation layer over the lower electrode layer. An intermediate ferroelectric material layer is formed have a substantially uniform amorphous phase on the un-patterned amorphous initiation layer. An anneal process is performed to change the intermediate ferroelectric material layer to a ferroelectric material layer having a substantially uniform orthorhombic crystalline phase. An upper electrode layer is formed over the ferroelectric material layer. One or more patterning processes are performed on the upper electrode layer, the ferroelectric material layer, the un-patterned amorphous initiation layer, and the lower electrode layer to form a ferroelectric memory device. An upper ILD layer is formed over the ferroelectric memory device, and an upper interconnect is formed to contact the ferroelectric memory device.

A multilayer structure, a capacitor structure and an electronic device are provided. The multilayer structure includes a first dielectric layer, a second dielectric layer and an intermediate dielectric layer. The intermediate dielectric layer is disposed between the first dielectric layer and the second dielectric layer. A material of the intermediate dielectric layer is represented by a formula of ABO, wherein A includes hafnium (Hf), zirconium (Zr), lanthanum (La) or tantalum (Ta), B includes lanthanum (La), aluminum (Al) or tantalum (Ta), A is different from B, O is oxygen, and x is a number less than 1 and greater than 0.

Multilayer structure, capacitor structure and electronic device

Various embodiments of the present disclosure are directed towards a memory device including a first bottom electrode layer over a substrate. A ferroelectric switching layer is disposed over the first bottom electrode layer. A first top electrode layer is disposed over the ferroelectric switching layer. A second bottom electrode layer is disposed between the first bottom electrode layer and the ferroelectric switching layer. The second bottom electrode layer is less susceptible to oxidation than the first bottom electrode layer.

Multi-layer electrode to improve performance of ferroelectric memory device

In some embodiments, the present disclosure relates to an integrated chip that includes one or more interconnect dielectric layers arranged over a substrate. A bottom electrode is disposed over a conductive structure and extends through the one or more interconnect dielectric layers. A top electrode is disposed over the bottom electrode. A ferroelectric layer is disposed between and contacts the bottom electrode and the top electrode. The ferroelectric layer includes a first lower horizontal portion, a first upper horizontal portion arranged above the first lower horizontal portion, and a first sidewall portion and coupling the first lower horizontal portion to the first upper horizontal portion.

In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a bottom electrode disposed over a substrate and a top electrode disposed over the bottom electrode. A ferroelectric switching layer is arranged between the bottom electrode and the top electrode. The ferroelectric switching layer is configured to change polarization based upon one or more voltages applied to the bottom electrode or the top electrode. A seed layer is arranged between the bottom electrode and the top electrode. The seed layer and the ferroelectric switching layer have a non-monoclinic crystal phase.

Growing community of inventors

Hsin-Chu, Taiwan

Yi Yang Wei