Cadence Design Systems, Inc.

Yi-Xiao Ding

Zhuo Li

Jhih-Rong Gao

Natarajan Viswanathan

Mehmet Can Yildiz

Sheng-En David Lin

Charles Jay Alpert

Derong Liu

Bentian Jiang

Wing-Kai Chow

Gracieli Posser

Wen-Hao Liu

Thomas Andrew Newton

William Robert Reece

Vitor Bandeira

Aspects of the present disclosure include system, methods, and software for buffer insertions. In one example, a method includes receiving a clock signal network layout, wherein the clock signal layout comprises a clock source electrically coupled to a plurality of clock sinks via a plurality of net segments, and creating a plurality of buffering solutions, wherein each buffering solution of the plurality of buffering solutions comprises a plurality of buffers inserted on one or more net segments of plurality of net segments. The method further includes assigning each buffering solution a timing delay value and an area value, and selecting a buffering solution of the plurality of buffering solutions based on the timing delay value and the area value. The method additionally includes committing the selected buffering solution into an integrated circuit design comprising the clock signal network.

Insertion delay and area tradeoff for buffering solution selection in clock tree synthesis

Aspects of the present disclosure include system, methods, and software for buffer insertions. In one example, a method includes receiving a clock signal network layout, the clock signal network layout comprising a clock source electrically coupled to a plurality of clock sinks via a plurality of net segments, a first hierarchy that bounds a first region of the clock signal network layout, and a second hierarchy that bounds a second region of the clock signal network layout. The method additionally includes creating a graph representative of the clock signal network layout, the graph comprising a plurality of logical edges, and identifying a to-be-inserted buffer location comprising a location on a net segment of the plurality of net segments to insert a buffer. The method further includes selecting a selected logical edge to insert the buffer based on the to-be-inserted buffer location, the first hierarchy, the second hierarchy, or a combination thereof.

Hierarchically-aware buffering for clock structures

Aspects of the present disclosure address systems and methods for driver resizing using a transition-based capacitance increase margin. An integrated circuit (IC) design stored in a database in memory is accessed. The IC design comprises a net comprising a set of driver cells. A capacitance increase margin for resizing an initial driver cell is determined based on a total capacitance of the net and transition time target associated with the initial driver cell. An alternative driver cell is selected from a library to resize the initial driver cell and is used to replace the initial driver cell in the net. The alternative driver is selected such that a pin capacitance of the alternative driver cell exceeds an initial pin capacitance corresponding to the initial driver cell by no more than the capacitance increase margin.

Driver resizing using a transition-based pin capacitance increase margin

A system includes a machine configured to perform operations including accessing an integrated circuit design including a buffer tree that interconnects a plurality of inputs and buffers. The buffer tree includes a baseline timing characteristic. The operations include identifying a set of candidate solutions for improving the baseline timing characteristic using an initial timing model and selecting a subset of candidate solutions that have a timing characteristic lower than the baseline timing characteristic. Then the subset of candidate solutions are evaluated using a detailed timing model and based on determining that at least one candidate solution in the subset has a timing characteristic that is better than the baseline timing characteristic, selecting a candidate solution from the set of candidate solutions, and updating the buffer tree based on the candidate solution.

Pruning redundant buffering solutions using fast timing models

Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of clock sinks during clock tree synthesis. An integrated circuit (IC) design comprising a clock net that includes a plurality of clock sinks is accessed. An initial number of clusters to generate from the set of clock sinks is determined using a machine-learning model. A first set of clusters is generated from the set of clocks sinks and includes the initial number of clusters. A timing analysis is performed to determine whether each cluster in the first set of clusters satisfies design rule constraints. The initial number of clusters is adjusted based on the timing analysis and a clustering solution is generated based on the adjusted number of clusters.

Machine-learning based clustering for clock tree synthesis

Various embodiments provide for clustering-based grouping of cells in a cell library, which can be used for pruning the cell library. In particular, various embodiments provide for a clustering-based grouping of cells in a cell library based on a criterion (or cell attribute), and for pruning of the cell library based on the grouping of cells, which can optimize the cell library for the criterion. For instance, some embodiments provide for a clustering-based grouping of cells based on leakage power and then applying cell library pruning to optimize for cell leakage power.

Grouping cells in cell library based on clustering

A system includes one or more processors and a computer storage medium storing instructions that cause a machine to perform operations including accessing an integrated circuit (IC) design including an initial clock tree. The operations include selecting a first driver to evaluate for resizing, the first driver being a first size and having a first leakage current and determining a baseline power consumption measurement of clock tree based on the first size and the first leakage current of the first driver. The operations include identifying a plurality of replacement drivers to replace the first driver and determining a power consumption measurement for a second driver. Based on determining that the power consumption measurement for the second driver is less than the baseline power consumption measurement replacing the first driver with the second driver and generating a layout instance based on the second driver.

Switching power aware driver resizing by considering net activity in buffering algorithm

An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a route connecting a source to a sink. A set of buffering candidates for buffering are generated for the net. A timing improvement associated with a buffering candidate in the set of buffering candidates is determined using a first timing model. The buffering candidate is pruned from the set of buffering candidates based on the timing improvement and a cost associated with the buffering candidate. The pruned set of buffering candidates is evaluated using a second timing model, and a buffering solution for the net is selected from the pruned set of buffering candidates based on a result of the evaluating. The IC design is updated to include the buffering solution selected for the net.

Pruning of buffering candidates for improved efficiency of evaluation

An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises a routing topology for a net comprising interconnections between a set of pins. The IC design further comprises a set of candidate locations for inserting buffers. A set of cells from a cell library in memory is accessed. A candidate location from the set of candidate locations is assessed to determine whether at least one cell in the set of cells fits at the location. Based on determining that at least one cell in the set of cells fits at the candidate location, the location is marked as bufferable. A largest cell width that fits at the candidate location is determined based on the set of cells and a buffering solution is generated for the net using the largest cell width as a constraint on buffer insertion performed at the candidate location.

Cell-width aware buffer insertion technique for narrow channels

An integrated circuit (IC) design is accessed from a database in memory. The IC design comprises an initial buffer tree for a net in the IC design. A maximum cost constraint for rebuffering the net is determined based on the initial buffer tree. A partial rebuffering solution is generated for net and a cost associated with the partial rebuffering solution is determined. Based on determining the cost of the partial rebuffering solution satisfies the maximum cost constraint, the partial rebuffering solution is saved in a set of partial rebuffering solutions for the net. A set of candidate rebuffering solutions for the net is generated based on the set of partial rebuffering solutions, and a rebuffering solution for the net is selected from the set of candidate rebuffering solutions. The database is updated to replace the initial buffer tree in the IC design with the rebuffering solution selected for the net.

Buffering algorithm with maximum cost constraint

Aspects of the present disclosure address systems and methods for performing a machine-learning based clustering of dock sinks during clock tree synthesis. An integrated circuit design comprising a clock net that includes a plurality of clock sinks is accessed. A set of clusters are generated by clustering the set of clock objects of the clock net. A machine-learning model is used to assess whether each cluster satisfies one or more design rule constraints. Based on determining each cluster in the set of dusters is assessed by the machine-learning model to satisfy the one or more design rule constraints, a timing analysis is performed to determine whether each cluster in the set of clusters satisfies the target timing constraints. A clustering solution for the clock net is generated based on the set of clusters in response to determining each cluster satisfies the one or more design rule constraints.

Machine-learning based prediction method for iterative clustering during clock tree synthesis

Various embodiments provide for layer assignment of a network of a circuit design based on a wirelength threshold, which can facilitate consideration of timing and electromigration and which may be part of electronic design automation (EDA) of a circuit design. More particularly, some embodiments determine (e.g., calculate) a wirelength threshold for a net (e.g., each net) of a circuit design based on one or more characteristics of the net, and select a layer for at least a portion of the net based on the wirelength threshold.

Layer assignment based on wirelength threshold

Various embodiments provide for layer assignment of a network of a circuit design based on a resistance or capacitance characteristic, such as a resistance/capacitance characteristic associated with a layer, a wire, or a via of the circuit design. In particular, various embodiments consider a resistance/capacitance characteristic of a layer, a wire, or a via of a circuit design to determine a set of layers for routing one or more networks of the circuit design, which can enable some embodiments to route the networks on the layers within a certain range that has very close resistance/capacitance (RC) characteristics, and can permit routing each network on layers having the smallest RC characteristic difference.

Layer assignment and routing based on resistance or capacitance characteristic

Various embodiments described herein provide for track assignment of wires of a network of a circuit design by dynamic programming. In particular, various embodiments use a dynamic programming process to determine a set of breaking points for a routing wire of a global-routed and layer-assigned circuit design, and to determine track assignments for each of the sub-wires (sub-routes) formed by applying the set of selected breaking points to the routing wire. This results in a set of track-assigned sub-wires (or track-assigned sub-routes), which various embodiments can connect together to generate a connected set of track-assigned sub-wires that can be used in place of the routing wire.

Track assignment by dynamic programming

Aspects of the present disclosure address improved systems and methods for buffer insertion in an integrated circuit (IC) design using a cost function that accounts for edge spacing and stack via constraints associated with cells in the IC design. An integrated circuit (IC) design comprising a routing topology for a net is accessed. A set of candidate insertion locations along the routing topology are identified. A set of buffering candidates is generated based on the candidate insertion locations. A buffering candidate comprises a cell inserted at a candidate insertion location along the routing topology. A cost associated with the buffering candidate is determined based on a number of potential edge spacing conflicts and a number of stack vias associated with the cell. A buffering solution for the net is selected from the buffering candidate based on the cost associated with the buffering candidate.

Growing community of inventors

Austin, TX, United States of America

Yi-Xiao Ding