United Microelectronics Corp.

Other

Chipbond Technology Corporation

Yi-Wen Chen

Chien-Ming Lai

Chien-Ting Lin

Che-Hua Hsu

Cheng-Hsien Chou

Chih-Hao Yu

Chun-Hsien Lin

Shih-Fang Tzou

Chen-Ming Huang

Zhi-Cheng Lee

Chi-Mao Hsu

Hsin-Fu Huang

Teng-Chun Tsai

Keng-Chu Lin

Yi-Wei Chen

En-Chiuan Liou

Ssu-I Fu

Yu-Ping Wang

Chan-Lon Yang

Li-Wei Feng

Shih-Hung Tsai

Chin-Fu Lin

Chun-Yuan Wu

Jyh-Shyang Jenq

Jiunn-Hsiung Liao

Yu-Hsiang Lin

Chih-Sen Huang

Chia-Lin Hsu

Chien-Chung Huang

Kun-Hsien Lin

Chih-Wei Yang

Jia-Rong Wu

Li-Wei Cheng

Tian-Fu Chiang

Guang-Hwa Ma

Tong-Jyun Huang

Jung-Tsung Tseng

Hung-Yi Wu

Ching-Ling Lin

Po-Cheng Huang

Cheng-Guo Chen

Po-Jui Liao

Jie-Ning Yang

Shao-Hua Hsu

Guang-Yaw Hwang

Tzung-Ying Lee

Tsung-Lung Tsai

Hung-Ling Shih

Wen-Han Hung

Nien-Ting Ho

Chao-Hung Lin

Shui-Yen Lu

Rai-Min Huang

Yu-Ru Yang

Min-Chuan Tsai

Chun-Tsen Lu

Chia-Fu Hsu

Ya-Huei Tsai

Chia-Chen Sun

Ying-Tsung Chen

Jian-Cun Ke

Yu-Chen Ma

Tsung-Yin Hsieh

Yu-Ting Tseng

Yin-Chen Lin

Ren-Peng Huang

Cheng-Yu Ma

Ching-Fu Lin

Yu-Feng Liu

Jian-Wei Chen

Chang-Yih Chen

Chien-An Chen

Ming-Hsiao Ke

Chih-Jung Su

Ta-Hua Hsieh

Hou-Hung Chou

Hsiao-Wen Lee

An interconnect for physically unclonable function (PUF), comprised of multiple arranged PUF cells. Each PUF cell includes at least two L-shaped metal line, wherein each L-shaped metal line includes a first part and a second part and is adjacent to a dummy metal line, and the first part of one L-shaped metal line is electrically connected to adjacent second part of another L-shaped metal line through via in vertical direction.

Interconnects for physically unclonable function and method of achieving physically unclonable function through interconnects

A ratchet driven screwdriver with bits storage has a body. A ratchet driving device has a ratchet, a lever, a ratchet housing, a ratchet spring, two L-shaped ratchets, a steel ball and a compression spring. A bits storage has a spring seat, two torsion springs, a storage tube, an axis column, and a bits box. When replacing the bits, the back cover is pulled to drive the storage tube. Currently, a pressure of the two torsion springs can extend to a tapered end of the axis column to release a vertical force, and the back cover is pulled apart. The two torsion springs extend to the other end of the axis column, and the vertical force can make the bits box pushed to the open state and locked, so that an alternate screwdriver bit can be selected with turning the back cover.

Ratchet driven screwdriver with bits storage

A preparation method of SiOaerogels is for solvent replacement process during preparation of SiOaerogels and adopts 'a manner of continuously circulation filtration' for an operation of adding solvent so that wet gel is continuously circulated and replaced (rinsing) by mass alcohol solvent and organic solvent to greatly accelerate (reducing) the time for replacement operation of wet gel solvent. At the same time, the alcohol solvent or the organic solvent passing through the reaction container separates wet gel from water content or the alcohol solution through filtration procedure. Afterward the alcohol solution and the organic solution enter the reaction container to perform solvent replacement such that fast continuously circulation filtration is performed to greatly improve the effect of replacing wet gel solvent.

Preparation method of SiO2 aerogels

A metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate adjacent to the metal gate. The metal gate includes a high-k dielectric layer, a bottom barrier metal (BBM) layer comprising TiSiN on the high-k dielectric layer, a TiN layer on the BBM layer, a TiAl layer between the BBM layer and the TiN layer, and a low resistance metal layer on the TiN layer.

Semiconductor device having metal gate structure

First and second semiconductor structures, a CESL, and an ILD layer are formed on a substrate. The first semiconductor structure includes first dummy gate, first nitride mask, and first oxide mask. The second semiconductor structure includes second dummy gate, second nitride mask, and second oxide mask. A first planarization is performed to remove a portion of the ILD layer, exposing CESL. A portion of the CESL, a portion of the ILD layer, the first and the second oxide masks are removed. A hard mask layer is formed on the first and the second nitride masks, and in a recess of the ILD layer. A second planarization is performed to remove a portion of the hard mask layer, the first and the second nitride masks, exposing first and second dummy gates. A remaining portion of the hard mask layer covers the ILD layer.

Method of fabricating semiconductor device

A method for fabricating a semiconductor device includes the following steps. Firstly, a dummy gate structure having a dummy gate electrode layer is provided. Then, the dummy gate electrode layer is removed to form an opening in the dummy gate structure, thereby exposing an underlying layer beneath the dummy gate electrode layer. Then, an ammonium hydroxide treatment process is performed to treat the dummy gate structure. Afterwards, a metal material is filled into the opening.

Method for fabricating semiconductor device

A method of removing a hard mask on a gate includes forming a first gate structure and a second gate structure. The first gate structure includes a first gate, a first hard mask disposed on the first gate and a first spacer surrounding the first gate and the first hard mask, wherein the second gate structure includes a second gate, a second hard mask disposed on the second gate and a second spacer surrounding the second gate and the second hard mask. Later, the first spacer surrounding the first hard mask and the second spacer surrounding the second hard mask are removed. After that, a dielectric layer is formed to cover the first hard mask and the second hard mask. Finally, the second dielectric layer, the first mask layer and the second mask layer are removed.

Method of removing a hard mask on a gate

A method of forming a semiconductor device is disclosed. A substrate having multiple fins is provided. An insulating layer fills a lower portion of a gap between two adjacent fins. At least one first stacked structure is formed on one fin and at least one second stacked structure is formed on one insulation layer. A first dielectric layer is formed to cover the first and second stacked structures. A portion of the first dielectric layer and portions of the first and second stacked structures are removed. Another portion of the first dielectric layer is removed until a top of the remaining first dielectric layer is lower than tops of the first and second stacked structures. A second dielectric layer is formed to cover the first and second stacked structures. A portion of the second dielectric layer is removed until the tops of the first and second stacked structures are exposed.

Method of forming semiconductor device

A method of manufacturing a metal gate is provided. The method includes providing a substrate. Then, a gate dielectric layer is formed on the substrate. A multi-layered stack structure having a work function metal layer is formed on the gate dielectric layer. An Oambience treatment is performed on at least one layer of the multi-layered stack structure. A conductive layer is formed on the multi-layered stack structure.

Oxygen treatment of replacement work-function metals in CMOS transistor gates

A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having an interlayer dielectric (ILD) layer thereon; forming a first recess, a second recess, and a third recess in the ILD layer; forming a material layer on the ILD layer and in the first recess, the second recess, and the third recess; performing a first treatment on the material layer in the first recess; and performing a second treatment on the material layer in the first recess and second recess.

Semiconductor device and method for fabricating the same

The semiconductor device includes a gate electrode, a first interlayer dielectric, a first mask layer, a second mask layer and a second interlayer dielectric. The first interlayer dielectric surrounds the periphery of the gate electrode, and the first mask layer is disposed on the gate electrode. The first mask layer and the gate electrode have at least one same metal component. The second mask layer is disposed on the sidewalls of the first mask layer, and the second interlayer dielectric is disposed on the second mask layer and in direct contact with the first interlayer dielectric.

Semiconductor device and manufacturing method thereof

A flexible substrate includes a base layer, a metallic layer, a solder mask layer and an identifying code, the metallic layer is disposed at a first surface of the base layer, the metallic layer comprises a plurality of traces and at least one bottom block used for defining marked position, wherein the traces and the at least one bottom block are covered with the solder mask layer, wherein above the perpendicular direction of the at least one bottom block of the metallic layer, a pre-marked area is defined on an exposing surface of the solder mask layer and by an outlined edge of the at least one bottom block, and the identifying code is formed within the pre-marked area of the solder mask layer.

Flexible substrate

A semiconductor structure and a manufacturing method thereof are disclosed. The semiconductor structure includes an isolation layer, a gate dielectric layer, a first work function metal, a first bottom barrier layer, a second work function metal, and a first top barrier layer. The isolation layer is formed on a substrate and has a first gate trench. The gate dielectric layer is formed in the first gate trench. The first work function metal is formed on the gate dielectric layer in the first gate trench. The first bottom barrier layer is formed on the first work function metal. The second work function metal is formed on the first bottom barrier layer. The first top barrier layer is formed on the second work function metal.

Semiconductor structure and manufacturing method of the same

A metal gate transistor is disclosed. The metal gate transistor includes a substrate, a metal gate on the substrate, and a source/drain region in the substrate. The metal gate further includes a high-k dielectric layer, a bottom barrier metal (BBM) layer on the high-k dielectric layer, a first work function layer on the BBM layer, a second work function layer between the BBM layer and the first work function layer, and a low resistance metal layer on the first work function layer. Preferably, the first work function layer includes a p-type work function layer and the second work function layer includes a n-type work function layer.

Metal gate transistor

A process for preparing ethylene glycol comprising: forming intermediums of formaldehyde and glycolaldehyde to synthetize ethylene glycol by reacting methanol with methanol in the presence of a catalyst composition comprising rhodium catalysts and ruthenium catalysts at a temperature between 50-150&#xb0; C. and a pressure between 0-40 kg/cmG.

Processes for preparing formaldehyde, glycolaldehyde and ethylene glycol

Growing community of inventors

Tainan, Taiwan

Yi-Wen Chen