Taiwan Semiconductor Manufacturing Comp. Ltd.

National Yang Ming Chiao Tung University

Yi-Wei Chiu

Li-Te Hsu

Tzu-Chan Weng

Cha-Hsin Chao

Chia-Ching Tsai

Chih-Teng Liao

Hung Jui Chang

Ying Ting Hsia

Xi-Zong Chen

Wan-Chun Kuan

Jeng Chang Her

Chin-Hsing Lin

Tsung Fan Yin

Chih Hsuan Cheng

Bo-Jhih Shen

Joung-Wei Liou

Yu-Chi Lin

Chih-Shan Chen

Yu-Wei Kuo

Yu Lun Ke

Meng-Je Chuang

Te-Chih Hsiung

Jen-Chih Hsueh

Yun-Yu Hsieh

Hua-Li Hung

Chi-Cheng Hung

Yu-Sheng Wang

Chen-Yuan Kao

Chih-Chang Hung

Yueh-Ching Pai

Chih-Hsuan Lin

Liang-Yueh Ou Yang

Ying-Ting Hsia

Tsung-Fan Yin

Han-Ting Tsai

Yi-Chun Chen

Cheng-Wei Chang

Cheng-Yi Wu

Shih-Ho Lin

Han-Ti Hsiaw

Shin-Yeu Tsai

Yu Shih Wang

Kuan-Cheng Wang

Chih-Hung Sun

Wan Hsuan Hsu

Yi-Tsang Hsieh

Yean-Zhaw Chen

Jr-Yu Chen

Chih-Lun Lu

I-Hsiu Wang

Wen-Cheng Wu

Jinn-Kwei Liang

Hsin-Yan Lu

Kuang-I Liu

Hsu-Yu Huang

Allen Ke

Wen-Zhong Ho

Hsin-Yi Tsai

Ching-Te Chuang

Shyh-Jye Jou

Po-Ju Chen

Ming-Hsien Tu

Chih-Ching Cheng

En-Ping Lin

Chia-Cheng Tai

Hung-Jui Chang

Y H Kuo

Kun-Cheng Chen

Fang-Yi Wu

Chin-Huei Chiu

Chen-Yi Liu

Chih-Hao Chen

Chun-Hung Liu

Wen-Yen Chen

Ching-Chung Su

Pin Chia Su

Kuo-Hsiu Wei

Kuo-Feng Huang

Chun-Hao Kung

Chen-Wei Pan

Yu-Li Lin

Chih-Cherng Jeng

Chia-Tsung Tso

Kaw-Wei Kuo

Yu-Lun Ke

Chi-Chin Hsu

Yih Song Chiu

Chia-Kai Sun

Chun-Hsing Wu

Wei-Chun Chen

Chen Yung-Chan

Meng-Chuan Wu

Yu-Lin Sung

Chia-Hsin Tai

Chung-Fan Huang

Chih-Hsiang Chu

Rong-Yu Wu

Chia-Hui Lee

Wu Meng-Chuan

Yu-Hao Hu

A semiconductor device includes first and second fin active regions extruding from a substrate, where the first and second fin active regions are separated by an isolation feature. The semiconductor includes a first gate stack disposed on the first fin active region and a second gate stack disposed on the second fin active region. The semiconductor device includes first source/drain features formed on the first fin active region, second source/drain features formed on the second fin active region, and a dielectric layer disposed along sidewalls of the first fin active region but not along sidewalls of the second fin active region. The first source/drain features extend vertically into the first fin active region at a first depth, the second source/drain features extend vertically into the second fin active region at a second depth, and the first depth is greater than the second depth.

Source and drain structure with reduced contact resistance and enhanced mobility

An integrated circuit structure includes a semiconductor substrate having a plurality of semiconductor strips, a first recess being formed by two adjacent semiconductor strips among the plurality of semiconductor strips, a second recess being formed within the first recess, and an isolation region being provided in the first recess and the second recess. The second recess has a lower depth than the first recess.

Method for forming recesses in a substrate by etching dummy fins

A method of forming a semiconductor device includes forming a source/drain region on a substrate and forming a first interlayer dielectric (ILD) layer over the source/drain region. The method further includes forming a second ILD layer over the first ILD layer, forming a source/drain contact structure within the first ILD layer and the second ILD layer, and selectively removing a portion of the source/drain contact structure to form a concave top surface of the source/drain contact structure.

Contact structure for semiconductor device

A method includes forming a transistor, which includes forming a gate dielectric on a semiconductor region, forming a gate electrode over the gate dielectric, and forming a source/drain region extending into the semiconductor region. The method further includes forming a source/drain contact plug over and electrically coupling to the source/drain region, and forming a gate contact plug over and in contact with the gate electrode. At least one of the forming the gate electrode, the forming the source/drain contact plug, and the forming the gate contact plug includes forming a metal nitride barrier layer, and depositing a metal-containing layer over and in contact with the metal nitride barrier layer. The metal-containing layer includes at least one of a cobalt layer and a metal silicide layer.

Metal gates of transistors having reduced resistivity

The present disclosure describes a method for forming a silicon-based, carbon-rich, low-k ILD layer with a carbon concentration between about 15 atomic % and about 20 atomic %. For example, the method includes depositing a dielectric layer, over a substrate, with a dielectric material having a dielectric constant below 3.9 and a carbon atomic concentration between about 15% and about 20%; exposing the dielectric layer to a thermal process configured to outgas the dielectric material; etching the dielectric layer to form openings; and filling the openings with a conductive material to form conductive structures.

Interlayer dielectric layer

A method includes forming a semiconductor fin extending a first height above a substrate, forming a dummy dielectric material over the semiconductor fin and over the substrate, forming a dummy gate material over the dummy dielectric material, the dummy gate material extending a second height above the substrate, etching the dummy gate material using multiple etching processes to form a dummy gate stack, wherein each etching process of the multiple etching processes is a different etching process, wherein the dummy gate stack has a first width at the first height, and wherein the dummy gate stack has a second width at the second height that is different from the first width.

Semiconductor device and method

A dielectric layer is formed over a substrate, an anti-reflective layer is formed over the dielectric layer, and a first hardmask is formed over the anti-reflective layer. A via opening and a trench opening are formed within the dielectric layer using the anti-reflective layer and the first hardmask as masking materials. After the formation of the trench opening and the via opening, the first hardmask is removed. An interconnect is formed within the openings, and the interconnect has a via with a profile angle of between about 70° and about 80° and a depth ratio of between about 65% and about 70%.

Semiconductor device and method of manufacture

Implementations of the present disclosure provide methods for preventing contact damage or oxidation after via/trench opening formation. In one example, the method includes forming an opening in a structure on the substrate to expose a portion of a surface of an electrically conductive feature, and bombarding a surface of a mask layer of the structure using energy species formed from a plasma to release reactive species from the mask layer, wherein the released reactive species form a barrier layer on the exposed surface of the electrically conductive feature.

Method of forming a barrier layer in an interconnect structure of semiconductor device

A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.

Magnetic tunnel junction device and method of forming same

A method includes forming a first semiconductor fin and a second semiconductor fin in a substrate, the first semiconductor fin adjacent the second semiconductor fin, forming a dummy gate structure extending over the first semiconductor fin and the second semiconductor fin, depositing a first dielectric material surrounding the dummy gate structure, replacing the dummy gate structure with a first metal gate structure, performing an etching process on the first metal gate structure and on the first dielectric material to form a first recess in the first metal gate structure and a second recess in the first dielectric material, wherein the first recess extends into the substrate, and wherein the second recess is disposed between the first semiconductor fin and the second semiconductor fin, and depositing a second dielectric material within the first recess.

Methods to form low-k dielectric materials for use as intermetal dielectrics in multilevel interconnect systems, along with their chemical and physical properties, are provided. The deposition techniques described include PECVD, PEALD, and ALD processes where the precursors such as TEOS and MDEOS may provide the requisite O-atoms and Ogas may not be used as one of the reactants. The deposition techniques described further include PECVD, PEALD, and ALD processes where Ogas may be used and, along with the Ogas, precursors containing embedded Si—O—Si bonds, such as (CHO)—Si—O—Si—(CHO)) and (CH)—Si—O—Si—(CH)may be used.

Interconnect system with improved low-K dielectrics

A chamber door, such as an etch chamber door may be heated during etch processing to, e.g., prevent etching by-products from adhering to the etch chamber door. Such heating of the etch chamber door, however, can impact the processing parameters and result in non-uniform processing, such as non-uniform etching characteristics across a semiconductor wafer, for instance. An insulator, such as an insulating film covering surfaces of the heated door, can reduce or eliminate transmission of heat from the door to a work piece such as a semiconductor wafer and this reduce or eliminate the non-uniformity of the process results.

Heat shield for chamber door and devices manufactured using same

A method includes forming an ILD to cover a gate stack of a transistor. The ILD and the gate stack are parts of a wafer. The ILD is etched to form a contact opening, and a source/drain region of the transistor or a gate electrode in the gate stack is exposed through the contact opening. A conductive capping layer is formed to extend into the contact opening. A metal-containing material is plated on the conductive capping layer in a plating solution using electrochemical plating. The metal-containing material has a portion filling the contact opening. The plating solution has a sulfur content lower than about 100 ppm. A planarization is performed on the wafer to remove excess portions of the metal-containing material. A remaining portion of the metal-containing material and a remaining portion of the conductive capping layer in combination form a contact plug.

Methods for forming contact plugs with reduced corrosion

A method of forming a gate structure includes forming an opening through an insulating layer and forming a first work function metal layer in the opening. The method also includes recessing the first work function metal layer into the opening to form a recessed first work function metal layer, and forming a second work function metal layer in the opening and over the first work function metal layer. The second work function metal layer lines and overhangs the recessed first work function metal layer.

Gate structure and method of forming the same

A device includes a substrate, a first dielectric layer over the substrate, a first conductive feature in the first dielectric layer, and an etch stop layer over the first dielectric layer. The etch stop layer includes metal-doped aluminum nitride. The device further includes a second dielectric layer over the etch stop layer, and a second conductive feature in the second dielectric layer. The second conductive feature extends into the etch stop layer and contacts the first conductive feature.

Interconnect structure of semiconductor device

Growing community of inventors

Kaohsiung, Taiwan

Yi-Wei Chiu