United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Au Optronics Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Cyntec Company

National Yang Ming Chiao Tung University

Other

Mediatek Singapore Pte. Ltd.

United Microelectroncis Corp.

Au Optrinics Corp.

Yi-Wei Chen

Tsun-Min Cheng

Chih-Chieh Tsai

Chih-Sen Huang

Pin-Hong Chen

Ching-Wen Hung

Tzu-Chieh Chen

Kai-Jiun Chang

Shih-Fang Tzou

Yi-An Huang

Jia-Rong Wu

Chia-Chen Wu

Yi-Hui Lee

Wei-Hsin Liu

Man-Ling Lu

Chao-Ching Hsieh

Chun-Chieh Chiu

Chung-Fu Chang

Yen-Liang Wu

Chia-Lung Chang

Chia-Jong Liu

Chih-Chien Liu

Nien-Ting Ho

Ching-Ling Lin

Ssu-I Fu

Yu-Hsiang Hung

Chi-Mao Hsu

Chien-Chung Huang

Kuo-Chih Lai

Hsin-Fu Huang

Po-Chun Chen

Teng-Chun Tsai

Chien-Ting Lin

Li-Wei Feng

Chia-Lin Lu

Ying-Cheng Liu

Ta-Wei Chiu

Feng-Yi Chang

Chun-Lung Chen

Chia-Wei Huang

Ying-Chiao Wang

Yung-Feng Cheng

Chen-Yi Weng

Jing-Yin Jhang

Kun-Yuan Liao

Yu-Ming Hsu

Chun-Hsien Lin

Shih-Hung Tsai

Chun-Hsien Huang

Chin-Chou Liu

Chih-Kai Hsu

Chin-Fu Lin

Chun-Yuan Wu

Jyh-Shyang Jenq

Po-Chao Tsao

Yu-Tse Kuo

Ming-Jui Chen

Chih-Wei Chao

Chao-Hung Lin

Shu-Ru Wang

Chien-Ting Ho

Neng-Hui Yang

Chien-Sen Weng

Yu-Shu Lin

Po-Cheng Huang

Ming-Tsung Chen

Kun-Chih Lin

Hsiao-Pang Chou

Yi-Sheng Cheng

Ta-Sung Lee

Mei-Ling Chen

Tsai-Fu Hsiao

Chun-Yao Yang

Yu-Cheng Tung

Chung-Hsing Wang

Chan-Lon Yang

Neng-Kuo Chen

I-Ming Tseng

Chieh-Te Chen

Chia-Lin Hsu

Chia-Hung Lin

Che-Chia Chang

An-Chi Liu

Kun-Ju Li

Chia-Chang Hsu

Zhi-Cheng Lee

Che-Hua Hsu

Chetan Deshpande

Min-Chuan Tsai

Yi-Wen Chen

Cheng-Guo Chen

Yu-Ting Li

Jei-Ming Chen

Tsung-Mu Yang

Wei-Pin Changchien

Po-Jui Liao

Fu-Shou Tsai

Jie-Ning Yang

Wen-Chin Lin

Shao-Hua Hsu

A method of forming a semiconductor memory device includes the following steps. First of all, a substrate is provided, and a plurality of gates is formed in the substrate, along a first direction. Next, a semiconductor layer is formed on the substrate, covering the gates, and a plug is then in the semiconductor layer, between two of the gates. Then, a deposition process is performed to from a stacked structure on the semiconductor layer. Finally, the stacked structure is patterned to form a plurality of bit lines, with one of the bit lines directly in contact with the plug.

Method of forming semiconductor memory device

A monitor wafer is provided. The monitor wafer includes a substrate and a cleaning layer. The cleaning layer is disposed on a bottom surface of the substrate. The cleaning layer is configured to remove particles from the substrate and/or a processing tool.

Monitor wafer and method of using the same

An electronic device, including an active device substrate, an insulation film, a vertical wire, and an anisotropic conductive adhesive, is provided. The active device substrate includes a substrate, a first wire, and a second wire. The first wire is configured on a first surface of the substrate, the second wire is configured on a second surface of the substrate, and a side surface connects the first surface to the second surface that is opposite to the first surface. The insulation film is configured on the side surface of the substrate. The vertical wire is configured on a surface of the insulation film and is located between the insulation film and the side surface of the substrate. The anisotropic conductive adhesive is configured between the vertical wire and the side surface of the substrate and electrically connects the vertical wire to the first wire and the second wire.

Electronic device and manufacturing method thereof

A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.

Buried word line of a dynamic random access memory and method for fabricating the same

The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).

Storage node contact structure of a memory device

A method for fabricating semiconductor device includes the steps of first forming a silicon layer on a substrate and then forming a metal silicon nitride layer on the silicon layer, in which the metal silicon nitride layer includes a bottom portion, a middle portion, and a top portion and a concentration of silicon in the top portion is greater than a concentration of silicon in the middle portion. Next, a conductive layer is formed on the metal silicon nitride layer and the conductive layer, the metal silicon nitride layer, and the silicon layer are patterned to form a gate structure.

Semiconductor device and method for fabricating the same

A pixel array substrate, including a substrate, multiple conductors, a pixel driving circuit, a first pad, and a second pad, is provided. The substrate has a first surface, a second surface, and multiple through holes. The through holes extend from the first surface to the second surface. The conductors are respectively disposed in the through holes. The pixel driving circuit is disposed on the first surface of the substrate. The first pad and the second pad are disposed on the second surface of the substrate. The conductors include a first conductor, a second conductor, and a first dummy conductor. The first conductor is electrically connected to the pixel driving circuit and the first pad. The second conductor is electrically connected to the pixel driving circuit and the second pad. The first dummy conductor is overlapped with and electrically isolated from the pixel driving circuit.

Pixel array substrate

The present disclosure provides an electronic device. The electronic device includes a first substrate, a second substrate opposite to the first substrate, a buffer layer disposed on the second substrate, a protection layer, an active array, a pixel array, and an alignment film. The first substrate includes a transmitting region, a display region surrounding the transmission region, and a periphery region surrounding the display region. The protection layer is disposed on the buffer layer. The active array is disposed on the buffer layer. The pixel array is disposed on the active array and electrically connected to the active array. The alignment film is conformally disposed on the protection layer and the second substrate. The alignment film includes a first portion in direct contact with the second substrate. A vertical projection of the first portion of the alignment film overlaps the transmitting region of the first substrate.

Electronic device

A display device, including a pixel array substrate and a sensor element substrate, is provided. The sensor element substrate overlaps the pixel array substrate, and includes a substrate, a switch element, and a photosensitive element. The switch element is located on the substrate. The photosensitive element is electrically connected to the switch element, and includes a transparent electrode, a sensing layer, a metal electrode, and a barrier layer. The sensing layer is located on the transparent electrode. The metal electrode is located on the sensing layer, and covers a first sidewall of the sensing layer. The barrier layer covers a first sidewall of the transparent electrode. The barrier layer is located between the metal electrode and the sensing layer, or between the transparent electrode and the sensing layer.

Display device

An electronic device includes a first substrate, a second substrate, a buffer layer, an active array, a pixel array, a protection layer and an alignment film. The first substrate includes a transmission region, a display region, and a periphery region. The periphery region surrounds the display region, and the display region surrounds the transmission region. The first substrate is disposed opposite to the second substrate. The buffer layer is disposed on the second substrate. The protection layer is disposed on the buffer layer, and a projection of the protection layer on the second substrate is apart from the transmission region. The active array is disposed on the buffer layer. The pixel array is disposed on the active array and is electrically connected to the active array. The alignment film is conformally disposed on the protection layer, the buffer layer, and the second substrate.

Electronic device and fabrication method of the same

Multi-stage content addressable memory devices are described. Some embodiments relate to memory devices including a plurality of rows of memory cells, multiple match lines and multiple pre-charge circuits. A first row of the plurality of rows includes a first segment and a second segment. The first segment may include a first subset of the memory cells of the first row and the second segment may include a second subset of the memory cells of the first row. The first match line is coupled to the memory cells of the first subset, and the second match line is coupled to the memory cells of the second subset. The first pre-charge circuit is configured to pre-charge the first match line to a first pre-charge voltage, and the second pre-charge circuit is configured to pre-charge the second match line to a second pre-charge voltage different from (e.g., greater than) the first pre-charge voltage.

Low-power multi-stage/multi-segment content addressable memory device

A fabricating method of a semiconductive element includes providing a substrate, wherein an amorphous silicon layer covers the substrate. Then, a titanium nitride layer is provided to cover and contact the amorphous silicon layer. Later, a titanium layer is formed to cover the titanium nitride layer. Finally, a thermal process is performed to transform the titanium nitride layer into a nitrogen-containing titanium silicide layer.

Bit line utilized in DRAM

Growing community of inventors

Taichung, Taiwan

Yi-Wei Chen