Analog Devices,inc.

Analog Devices Global

Analog Devices International Unlimited Company

Yi Wang

Yiming Zhao

Reuben Pascal Nelson

Dan Zhu

James Hand

Guanghua Man

Xiaopeng Song

Apparatus and methods for asynchronous clock mapping are provided herein. In certain configurations, an upstream server of a transport network generates clock difference data indicating a time difference between a server clock signal and a client clock signal, which have an asynchronous timing relationship with respect to one another. The clock difference data is generated with high precision by using one or more time-to-digital converters (TDCs). The clock difference data is included in a transmitted data stream, and is used by a downstream server to recover client information with enhanced accuracy.

Apparatus and methods for asynchronous clock mapping

Aspects of this disclosure relate to reference switchover. In one embodiment, an apparatus includes a phase error detector, a phase alignment detector, and a selection circuit. The phase error detector is configured to generate an indication of a relative phase difference between a first reference clock signal and a second reference clock signal. The phase alignment detector is configured to receive the indication of the relative phase difference and determine when the relative phase difference satisfies a preset threshold. The selection circuit is configured to transition from providing the first reference clock signal as a clock system reference signal to providing the second reference clock signal as the clock system reference signal responsive to the phase alignment detector detecting that the relative phase difference satisfies the preset threshold.

Redundant clock switchover

Synthesizers are configured with first and second phase-locked loops (PLL's). The first PLL is arranged to include a digitally-controlled oscillator (DCO) and to respond to an input signal to provide a reference signal with a plurality of selectable reference frequencies. The second PLL is arranged to include a voltage-controlled oscillator (VCO) to thereby provide output signals in response to the reference signal. This synthesizer structure is particularly effective when responding to a noisy input signal as may be the case, for example, in wireless communication systems that provide a network clock to transceivers through lengthy optical links.

Frequency synthesizers for wireless communication systems

An amplifier circuit includes a first operational amplifier having an inverting input and a non-inverting input. The non-inverting input receives an input signal, and the inverting input is connected to a noise generating system. The amplifier circuit further includes a second operational amplifier having an inverting input and a non-inverting input. The non-inverting input of the second operational amplifier receives an input signal, and the inverting input is connected to a noise generating system. A differential in/out operational amplifier, in the amplifier circuit, has an inverting input connected to an output of the second operational amplifier and a non-inverting input connected to an output of the first operational amplifier. The noise generating system injects a narrow band noise into a differential amplifier with no insertion loss and mismatching along the signal path. The narrow band noise is obtained by amplifying thermal noise of an amplifier. The amplified thermal noise is bandwidth limited. The bandwidth limited amplified thermal noise is filtered by a low pass a filter.

Differential intermediate frequency (IF) amplifier with narrow band noise dithering for driving high speed analog-to-digital conversion and communication applications

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Reidsville, NC, United States of America

Yi Wang