Vanguard International Semiconductor Corporation

Yi-Tsung Jan

Chih-Cherng Liao

Wen-Tsung Wang

Sung-Min Wei

Yuan-Heng Li

Zhe-Xiong Wu

Chih-Ming Kao

Rong-Gen Wu

Ting-Yu Kuo

Peng-Fei Wu

Su-Chen Lin

You-Cheng Liau

Mao-Tsang Chen

Wen-Jen Chuang

Huan-Yu Chien

Mao-Tsung Chen

A method for manufacturing a contact plug is provided. The method includes providing a silicon substrate having at least one opening. A titanium layer is conformably formed in the opening. A first barrier layer is conformably formed on the titanium layer in the opening. A rapid thermal process is performed on the titanium layer and the first barrier layer. After performing the rapid thermal process, a second barrier layer is conformably formed on the first barrier layer in the opening.

Contact plug and method for manufacturing the same

A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed on the semiconductor substrate, and a hard mask layer formed on the gate. A first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate equal to half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer and the hard mask layer as masks.

Method for fabricating source/drain devices

A method for fabricating source/drain devices. A semiconductor substrate is provided with a gate formed thereon, a first doped area is formed on a first side of the gate on the semiconductor substrate, and a second doped area is formed on a second side of the gate on the semiconductor substrate in a manner such that the second doped area is separated from the gate by a predetermined distance. A patterned photo resist layer is formed on the semiconductor substrate having an opening on the second side, the exposed gate less than half the width of the gate. The semiconductor substrate is implanted and annealed to form a dual diffusion area on the second side of the gate using the patterned photo resist layer as a mask.

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Taipei, Taiwan

Yi-Tsung Jan