Taiwan Semiconductor Manufacturing Comp. Ltd.

Industrial Technology Research Institute

National Taiwan University

Yi-Ting Cheng

Juei-Nai Kwo

Hsien-Wen Wan

Yu-Jie Hong

Ruoh-Huey Uang

Ming-Hwei Hong

Bo-Yu Yang

Tzong-Ming Lee

Kuo-Chan Chiou

Minghwei Hong

Yu-Ming Wang

Tun-Wen Pi

A method includes forming a semiconductive channel layer on a substrate. A dummy gate is formed on the semiconductive channel layer. Gate spacers are formed on opposite sides of the dummy gate. The dummy gate is removed to form a gate trench between the gate spacers, resulting in the semiconductive channel layer exposed in the gate trench. A semiconductive protection layer is deposited in the gate trench and on the exposed semiconductive channel layer. A top portion of the semiconductive protection layer is oxidized to form an oxidation layer over a remaining portion of the semiconductive protection layer. The oxidation layer is annealed after the top portion of the semiconductive protection layer is oxidized. A gate structure is formed over the semiconductive protection layer and in the gate trench after the oxidation layer is annealed.

Semiconductor device and manufacturing method thereof

A semiconductor device includes a substrate, a semiconductor fin, a silicon layer, a gate structure, gate spacers, and source/drain structures. The semiconductor fin is over the substrate. The silicon layer is over the semiconductor fin. The gate structure is over the silicon layer, in which the gate structure includes an interfacial layer over the silicon layer, a gate dielectric layer over the interfacial layer, and a gate electrode over the gate dielectric layer. The gate spacers are on opposite sidewalls of the gate structure and in contact with the interfacial layer of the gate structure, in which a bottom surface of the interfacial layer is higher than bottom surfaces of the gate spacers. The source/drain structures are on opposite sides of the gate structure.

A semiconductor device includes a semiconductive channel region, a semiconductive protection layer, a gate structure, and a pair of gate spacers. The semiconductive protection layer is on and in contact with the channel. The gate structure is above the semiconductive protection layer and includes gate dielectric layer and a gate electrode. The gate dielectric layer is above the semiconductive protection layer. The gate electrode is above the gate dielectric layer. The gate spacers are on opposite sides of the gate structure. The semiconductive protection layer extends from an inner sidewall of a first one of the pair of gate spacers to an inner sidewall of a second one of the pair of gate spacers.

A method for forming a micro bump includes forming a first nano-particle layer on a substrate and forming a second nano-particle layer on the first nano-particle layer. The first and second nano-particle layers include a plurality of first nano particles and a plurality of second nano particles, respectively. The method further includes irradiating a laser beam onto the second nano-particle layer, where the laser beam penetrates through the second nano-particle layer and is at least partially absorbed by at least some of the first nano particles to generate heat. The first nano particles and the second nano particles have different absorption rates with respect to the laser beam.

Micro bump and method for forming the same

A method for manufacturing a substrate with surface substrates by employing photothermal effect is described. Nanoparticles on the surface of the substrate excited by a beam convert light energy to thermal energy. The surface structure on the substrate is formed through the thermal energy generated by the excited nanoparticles. The substrate with plural pores is thus formed.

Growing community of inventors

Kaohsiung, Taiwan

Yi-Ting Cheng