United Microelectronics Corp.

Fujian Jinhua Integrated Circuit Co., Ltd.

Advanced Semiconductor Engineering, Inc.

Footprintku Inc.

Yi-Ting Chen

En-Chiuan Liou

Sho-Shen Lee

Chun-Hung Lin

Hsiao-Lin Hsu

Chien-Hao Chen

Chun-Chi Yu

Chia-Hung Wang

Yuan-Chi Pai

Chia-Hsun Tseng

Teng-Chin Kuo

Yung-Hsing Chang

Tuan-Yen Yu

Wen-Hsin Lin

Yan-Jhih Wang

Shih-Wei Chan

Jun-Qiang Wei

Yu-Siang Fan Jiang

Chia-Chang Hsu

Yi-Jing Wang

Che-Yi Lin

Mong-Fong Horng

Shih-Feng Huang

Cheng-Ta Lu

Jhao-Hao Lee

Po-Tsang Chen

Chun-Chieh Tsai

Jiun-Huei Ho

Chun-Ting Lu

Lu-Wei Kuo

Zheng-Feng Chen

Yi-Chih Chiang

Kuan-Hsiang Tseng

Tzung-Pei Hong

An image object classification method and system are disclosed. The method is executed by a processor coupled to a memory. The method includes: providing an image file including at least one image object, performing a process of extracting multiple binary-classified characteristics on the image object to obtain a plurality of first results independent of each other in categories, combining the plurality of first results in a manner of dimensionality reduction based on concatenation, performing a process of characteristics abstraction on the combined first results to obtain a second result, and performing a process of characteristics integration on the plurality of first results and the second result in a manner of dot product of matrices to obtain a classification result.

Image object classification method, system and computer readable medium

A method of forming a layout of a semiconductor device includes the following steps. First line patterns extend along a first direction in a first area and a second area, but the first line patterns extend along a second direction in a boundary area. Second line patterns extend along a third direction in the first area and the second area, but the second line patterns extend along a fourth direction in the boundary area, so that minimum distances between overlapping areas of the first line patterns and the second line patterns in the boundary area are larger than minimum distances between overlapping areas of the first line patterns and the second line patterns in the first area and the second area. A trimming process is performed to shade the first line patterns and the second line patterns in the boundary area and the second area.

Method of forming layout of semiconductor device

A method of forming an overlay mark structure includes the following steps. An insulation layer is formed on a substrate. A first overlay mark is formed in the insulation layer. A metal layer is formed on the substrate. The metal layer covers the insulation layer and the first overlay mark. The metal layer on the first overlay mark is removed. A top surface of the first overlay mark is lower than a top surface of the insulation layer after the step of removing the metal layer on the first overlay mark. A second overlay mark is formed on the metal layer. In the method of forming the overlay mark structure, the first overlay mark may not be covered by the metal layer for avoiding influences on related measurements, and the second overlay mark may be formed on the metal layer for avoiding related defects generated by the height difference.

Method of forming overlay mark structure

A measurement make includes four rectangular regions having a first region and a second region arranged diagonally, and a third region and a fourth region arranged diagonally. A plurality sets of first inner pattern blocks, first middle pattern blocks, and first outer reference pattern blocks, are disposed within the first region. Each first inner pattern block comprises line patterns and a block pattern. The block pattern has multiple space patterns arranged therein. The first inner pattern block is rotational symmetrical to the first middle pattern block.

Method for monitoring semiconductor process

An electronic component footprint verification system and a method thereof are provided in the present disclosure. The system is available to an external user for selecting an electronic component footprint to be verified, reading a verification rule checklist in an external database, extracting characteristics of the electronic component footprint, accessing characteristic data from the electronic component footprint, verifying the characteristic data based on the verification rule checklist, and displaying a verification result.

Electronic component footprint verification system and a method thereof

An automated electronic component footprint setup system and a method thereof are provided in the present disclosure. The system is available to not only an external first user for configuring characteristic parameters of an electronic component for the database but also an external second user for configuring setup parameters of an electronic component footprint to be created. Then, the system is to create an electronic component footprint of a specific electronic layout system according to the characteristic parameters of the electronic component, component setup regulations and the setup parameters, all of which correspond to the electronic component footprint.

Automated electronic component footprint setup system and a method thereof

A semiconductor process includes: applying an encapsulation material on an upper surface of a first substrate to encapsulate a die and first conductive parts, wherein the encapsulation material is a B-stage adhesive; forming a plurality of openings on the encapsulation material to expose the first conductive parts; pressing a second substrate onto the encapsulation material to adhere a lower surface of the second substrate to the encapsulation material, wherein the second substrate includes second conductive parts, and each of the first conductive parts contacts a corresponding one of the second conductive parts; and heating to fuse the first conductive parts and the corresponding second conductive parts to form a plurality of interconnection elements and solidify the encapsulation material to form a C-stage adhesive.

Semiconductor package structure and semiconductor process

Measurement mark and method for monitoring semiconductor process

The present disclosure relates to a semiconductor package structure and semiconductor process. The semiconductor package includes a first substrate, a second substrate, a die, a plurality of interconnection elements and an encapsulation material. Each of the interconnection elements connects the first substrate and the second substrate. The encapsulation material encapsulates the interconnection elements. The encapsulation material defines a plurality of accommodation spaces to accommodate the interconnection elements, and the profile of each accommodation space is defined by the individual interconnection element, whereby the warpage behavior of the first substrate is in compliance with that of the second substrate during reflow.

A method of forming an integrated circuit includes the following steps. A substrate including a plurality of exposure fields is provided, and each of the exposure field includes a target portion and a set of alignment marks. Measure the set of alignment marks of each exposure field by a measuring system to obtain alignment data for the respective exposure field. Determine an exposure parameter corresponding to each exposure field and an exposure location on the target portion from the alignment data for the respective exposure field by a calculating system. Feedback the alignment data to a next substrate.

Method of forming integrated circuit

A manufacturing method of a pattern transfer mask includes the following steps. A basic mask is provided. The basic mask includes a plurality of patterns formed by a patterned absorber layer on a substrate according to a first writing layout. A photolithographic process is then performed by the basic mask to obtain individual depth of focus (iDoF) ranges of each of the patterns and a usable depth of focus (UDoF) range of the patterns. At least one constrain pattern dominating the UDoF range is selected from the patterns in the basic mask. The rest of the patterns except the constrain pattern are non-dominating patterns. A second writing layout is then generated for reducing a thickness of the patterned absorber layer in the constrain pattern or in the non-dominating patterns.

Manufacturing method of pattern transfer mask

Described herein are semiconductor packages having an insulating layer and the manufacturing methods thereof, wherein semiconductor packages include a die pad; a plurality of leads surrounding the die pad, wherein each of the leads comprises an inner lead portion and an outer lead portion, and wherein at least one lead further comprises a trace portion; a chip disposed on the die pad and electrically connected to the leads; a molding compound encapsulating the chip, the inner lead portions and the trace portion, where the outer lead portions and a first surface of the trace portion are exposed from the molding compound; and an insulating layer covering the first surface of the trace portion.

Semiconductor packages and related manufacturing methods

An overlap mark set is provided to have at least a first and a second overlap marks both of which are located at the same pattern layer. The first overlap mark includes at least two sets of X-directional linear patterns, having a preset offset atherebetween; and at least two sets of Y-directional linear patterns, having the preset offset atherebetween. The second overlap mark includes at least two sets of X-directional linear patterns, having a preset offset btherebetween; and at least two sets of Y-directional linear patterns, having the preset offset btherebetween. The preset offsets aand bare not equal.

Overlap mark set and method for selecting recipe of measuring overlap error

An overlay mark applied to a LELE-type double patterning lithography (DPL) process including a first lithography step, a first etching step, a second lithography step and a second etching step in sequence is described. The overlay mark includes a first x-directional pattern and a first y-directional pattern of a previous layer, second x-directional and y-directional patterns of a current layer defined by the first lithography step, and third x-directional and y-directional patterns of the current layer defined by the second lithography step. The second x-directional patterns and the third x-directional patterns are arranged alternately beside the first x-directional pattern. The second y-directional patterns and the third y-directional patterns are arranged alternately beside the first y-directional pattern.

Overlay mark and method for forming the same

An overlay mark is described, including N (N&#x2267;2) groups of first x-directional linear patterns each defined from a different one of N pre-layers, N groups of second x-directional linear patterns of a current layer, N groups of first y-directional linear patterns each defined from a different one of the N pre-layers, and N groups of second y-directional linear patterns of the current layer. Each group of second x-directional linear patterns is disposed together with one group of first x-directional linear patterns, wherein the second linear patterns and the x-directional linear patterns are arranged alternately. Each group of second y-directional linear patterns is disposed together with one group of first y-directional linear patterns, wherein the second linear patterns and the first linear patterns are arranged alternately.

Growing community of inventors

Kaohsiung, Taiwan

Yi-Ting Chen