Macronix International Co., Ltd.

Yi-Te Shih

Chun-Hsiung Hung

Chung-Kuang Chen

Chung Kuang Chen

Hsiang-Pang Li

Ful-Long Ni

Chun-Shiung Hung

A memory device comprises first memory block having first boundary cell and second memory block having second boundary cell. Data of the first and the second boundary cells are outputted simultaneously corresponding to a plurality of column selection signals.

Memory Device

A data sensing method for sensing storage data stored in a memory cell includes the steps of: biasing a sensing node and a reference node to a first voltage in response to a first control signal; discharging the sensing node and the reference node via the memory cell and a reference memory cell, respectively; enabling a latch circuit to amplify a voltage difference between the sensing node and the reference node.

Sense amplifier with a sensing transmission transistor and a reference transmission transistor operating in saturation regions and data sensing method thereof

A data sensing method for sensing data stored in first and second memory cells includes the steps of: setting a first voltage according to a bit-line voltage corresponding to the first memory cell in response to an enabled level of a first clock signal; providing the first voltage as a sensing voltage in response to a disabled level of the first clock signal; comparing the sensing voltage with a reference voltage to generate a first output voltage; setting a second voltage according to a bit-line voltage corresponding to the second memory cell in response to an enabled level of a second clock signal, a phase difference between the first and second clock signals being 180 degrees; providing the second voltage as the sensing voltage in response to a disabled level of the second clock signal; and comparing the sensing voltage with the reference voltage to generate a second output voltage.

Sense amplifier and data sensing method thereof

A memory comprises a memory array, a sense unit, and a biasing and shielding circuit. The biasing and shielding circuit is coupled to the memory array and the sense unit, wherein the biasing and shielding circuit comprises a first transistor, a second transistor, and a capacitor. The first transistor has a gate coupled to a biasing voltage and a first terminal coupled to the sense unit. The second transistor has a gate coupled to the biasing voltage and a first terminal coupled to a first potential. The capacitor is coupled to the sense unit and the first transistor.

Memory and method operating the memory

A multiple-stage charge pump circuit comprises first and second pump capacitors, first and second transfer circuits, first and second driving circuits, and a charge recycle circuit. The first pump capacitor, the first transfer circuit, and the first driving circuit form a first stage circuit, and the second pump capacitor, the second transfer circuit and the second driving circuit form a second stage circuit. The first and the second stage circuits operate 180 degree out of phase with each other. The charge recycle circuit transfers the charge at the second end of the first pump capacitor to the second end of the second pump capacitor in a first time interval, and transferring the charge at the second end of the second pump capacitor to the second end of the first pump capacitor in a second time interval.

Multiple-stage charge pump with charge recycle circuit

A circuit including a first data selection circuit and a second data selection circuit for transmitting a data stream is provided. The first data selection circuit having first controllable channels turns on a first operating channel being one of the first controllable channels in an odd-numbered period and turns off the first controllable channels in an even-numbered period adjacent to the odd-numbered period for transmitting a first bit datum of the data stream. The second data selection circuit having second controllable channels turns off the second controllable channels in the odd-numbered period and turns on a second operating channel being one of the second controllable channels in the even-numbered period for transmitting a second bit datum of the data stream.

Circuit and method for transmitting data stream

A control circuit applied in a memory that comprises a first memory block and a second memory block, and each of the first and the second memory blocks includes a boundary cell. The control circuit comprises an address decoder, a first Y-multiplexer, and a second Y-multiplexer. The address decoder provides a plurality of column selection signals capable of being a boundary value. The first Y-multiplexer corresponds to the first memory block and provides a first boundary data channel for a boundary cell of the first memory block. The second Y-multiplexer corresponds to the second memory block and provides a second boundary data channel for a boundary cell of the second memory block. The first and the second boundary data channels are enabled simultaneously in response to the boundary value for outputting boundary data stored in the boundary cell of the first memory block and that of the second memory block.

Memory control circuit and memory accessing method

A multiple-stage charge pump circuit includes first and second pump capacitors, a charge recycle circuit, and first and second transfer circuits. The charge recycle circuit includes first and second driving circuits and a switch circuit turning off to make a node floating and to couple first terminals of the first and second pump capacitors to the node in a first time period. The switch circuit and first and second driving circuits provide a specific voltage to the node and control voltages at the first terminals of the first and second pump capacitors in second and third time periods, respectively. The first and second transfer circuits provide a high voltage to a second terminal of the first pump capacitor in the second time period, and provide the voltage of the second terminal of the first pump capacitor to a second terminal of the second pump capacitor in the third time period.

Multiple-stage charge pump circuit with charge recycle circuit

A controlling method of a voltage regulator is provided. The voltage regulator at least includes a differential circuit and a pump high-voltage circuit which has a bias path, an output transistor and an output terminal. The controlling method includes steps of: providing at least a pre-charge path to the pump high-voltage circuit, closing the bias path and charging the output terminal with the pre-charge path when the output terminal is transient, detecting an output level of the output terminal, and closing the pre-charge path and open the bias path to bias the output transistor when the output level reaches a predetermined value.

Output transient responsive voltage regulator controlling apparatus and method

One or more clock signals are used to control sense amplifier measurements. For example, multiple threshold voltage measurement types characterize the multiple clock signals, and selecting the appropriate clock signal selects the appropriate measurement type. In another example, multiple clock signals control multiple measurements of a particular location of nonvolatile memory, so that one of multiple clock signals is selected or the appropriate clock signal is generated to apply an appropriate threshold voltage window sensitivity.

Method and apparatus to control sensing time for nonvolatile memory

A shielding circuit for preventing a sense current of a target cell from the influence of a source current of first adjacent cell includes a pre-discharge device, first and second biasing units, first and second voltage pull-down units, and a connection units. The pre-discharge device is for setting the voltage of the sense node to a negative voltage. The first and second biasing units are for biasing the source voltage of the target and the first adjacent cell equal to a biasing voltage, respectively. The first and second voltage pull-down units are for pulling down the source voltage of the target and the first adjacent cell closing to a ground level, respectively. The connection unit is for receiving and outputting the sense current passing through the first biasing unit to the sense node.

Biasing and shielding circuit for source side sensing memory

Methods and apparatuses are disclosed for programming a page of nonvolatile memory cells across multiple nonvolatile memory cells accessed by multiple word lines.

Method and apparatus for fast programming of memory

A circuit and method for speed and stability enhancement for a sense amplifier comprises an offset current apparatus and a discharge current apparatus connected to a data node on one side of a transmission transistor that has another side with a sense node connected to a charge current apparatus and a leakage current apparatus with the leakage current mirrored from the offset current. The offset current ensures the transmission transistor not shut down and the voltage on the data node below a specific level, thereby enhancing the speed of the sense amplifier. The leakage current enhances the stability of the sense amplifier. Mirroring the leakage current from the offset current results good control of the operation and performance of the sense amplifier.

Growing community of inventors

Zhubei, Taiwan

Yi-Te Shih