Au Optronics Corporation

Yi-Suei Liao

Chien-Liang Chen

Hao-Chieh Lee

Kuan-Yu Chen

Wei-Li Lin

Ming-Yen Tsai

Jian-Hong Lin

Chen-Lun Chiu

Chao-Ching Hsu

Chun-Huan Chang

Kai-Yuan Siao

Chien-Feng Chiu

Yih-Jen Hsu

Mien-Mien Cheng

A display panel includes a display area, a shift register circuit, a first start signal line, and a second start signal line. The shift register circuit is electrically coupled to the display area through a plurality of signal output lines. The first start signal line and the second start signal line are electrically coupled to the shift register circuit. The first start signal line and the second start signal line are both arranged without crossing the signal output lines.

Display panel and method for manufacturing the same

A display panel and an active device thereof are provided. The active device includes a gate, a semiconductor layer, a first source and a plurality of first drains. The first source includes a first side and a second side opposite to each other, the first side has a plurality of first recesses, and the second side has a plurality of second recesses. Each of the first recesses and a corresponding second recess are disposed opposite to each other to constitute a recess-pair. A minimum distance between the first recess and the second recess of each recess-pair is A, a minimum distance between two neighboring recess-pairs is B, wherein A is greater than B. The first drains are electrically connected to each other, and each of the first drains is respectively disposed in one of the recesses of the first source.

Display panel and active device thereof

A liquid crystal display panel including a first substrate, an active device array, a gate driver on array (GOA), at least one signal transmission connection pad, a second substrate, an opposite electrode layer, conduction devices, and a display medium is provided. The active device array includes scan lines, data lines, and active devices. The GOA is electrically connected to the scan lines. The signal transmission connection pads are located respectively at a first side of the active device array and a second side of the active device array. The first side and the second side are corresponding to two opposite ends of the scan lines, respectively. The conduction devices and the display medium are disposed between the first substrate and the second substrate. The signal transmission connection pads are electrically connected to the opposite electrode layer through the conduction devices.

Display panel

By way of enabling a reset signal while turning off a liquid crystal display, a method for decaying residual image of the liquid crystal display is capable of setting the corresponding gate signal of each of a plurality of gate lines of the liquid crystal display based on the reset signal being enabled. Accordingly, enhanced discharging processes on all the storage units of the liquid crystal display for fast decaying residual image can be performed via the data switches of the liquid crystal display turned on by the gate signals being set. The reset operation for performing discharging processes in response to the reset signal can be carried out based on a reset circuit for setting all the gate signals to become high-level signals, or based on a charging/discharging module for furnishing a high-level voltage directly to all the gate lines.

Liquid crystal display device and method for decaying residual image thereof

An LCD device is configured to drive a plurality of shift register units using two clock signals having different driving abilities. Each shift register unit may thus generate a stronger signal for triggering a next-stage shift register unit, thereby improving cold-start. When the LCD device has been activated over a predetermined period of time, the driving ability of the clock signal having higher driving ability is gradually lowered, thereby reducing power consumption.

LCD driving circuit in which shift register units are driven by a first clock signal of fixed duty/amplitude and a second clock signal of variable duty/amplitude

A LCD panel includes an invisible zone and a visible zone. The invisible zone includes a gate driver and a wiring zone, wherein the gate driver sequentially outputs six pulse signals. By the wiring zone, a first pulse signal is converted into a first gate driving signal of the visible zone, a second pulse signal is converted into a fourth gate driving signal of the visible zone, a third pulse signal is converted into a fifth gate driving signal of the visible zone, a fourth pulse signal is converted into a second gate driving signal of the visible zone, a fifth pulse signal is converted into a third gate driving signal of the visible zone, and a sixth pulse signal is converted into a sixth gate driving signal of the visible zone.

LCD panel with visible zone of dual-gate thin film transistor array

A display panel includes an active device array substrate, an opposite substrate, and a liquid crystal layer. The active device array substrate includes a substrate and further includes a pixel array, signal lines, and first and second repairing lines all disposed on the substrate. The signal lines electrically connect the pixel array. The first repairing line includes first and second line segments respectively located on first and second sides of the pixel array. The first side is substantially perpendicular to the second side. The first and second line segments are electrically connected. The second repairing line includes third and fourth line segments respectively located on third and second sides of the pixel array. The third side is substantially parallel to the first side. The fourth and third line segments are electrically connected. The opposite substrate above the active device array substrate does not cover the first and third line segments.

A flat panel display, a shift register with image retention release and method for releasing image retention are provided. An output end of the shift register couples to a gate line of a display panel. A first end of a first transistor couples to the output end of the shift register. A second end of the first transistor couples to a system voltage VDD or a reference voltage VSS. A first end of a capacitor couples to a control end of the first transistor. A second end of the capacitor couples to the reference voltage VSS. During a power-off period, the reference voltage VSS is pulled high for turning on the first transistor, therefore the voltage of the gate line is pulled high.

Shift register with image retention release and method for image retention release

By way of enabling a reset signal while turning off a liquid crystal display, a method for decaying residual image of the liquid crystal display is capable of setting the corresponding gate signal of each of a plurality of gate lines of the liquid crystal display based on the enabled reset signal. Accordingly, enhanced discharging processes on all the storage units of the liquid crystal display for fast decaying residual image can be performed via the data switches of the liquid crystal display turned on by the gate signals being set. The reset operation for performing discharging processes in response to the reset signal can be carried out based on a reset circuit for setting all the gate signals to become high-level signals, or based on a charging/discharging module for furnishing a high-level voltage directly to all the gate lines.

Liquid crystal display device with charging and discharging module

A flat display device includes an array substrate. The array substrate includes a plurality of gate lines, data lines and pixels. The pixels include a plurality of first pixel units and second pixel units, and each of the first pixel units and each of the second pixel units include more than three pixels. The first pixel units and the second pixel units disposed in between two adjacent data lines are arranged alternately, wherein the first pixel units are electrically connected with one of the two adjacent data lines, and the second pixel units are electrically connected with the other data line.

Array substrate and flat display device

An LCD device includes a plurality of gate lines and a plurality of shift register units for driving corresponding gate lines. Each shift register unit includes a first circuit and a second circuit. The first circuit, disposed on a first side of a corresponding gate line, includes a pulse generator and a first transistor having a first W/L ratio. The pulse generator provides a driving signal according to the voltage obtained at a node, while the first transistor maintains the voltage level of the node. The second circuit, disposed on a second side of the corresponding gate line, includes a second transistor having a second W/L ratio. The second transistor maintains the voltage level of the driving signal from the second side of the corresponding gate line. The first W/L ratio is smaller than the second W/L ratio, and the first circuit occupies larger space than the second circuit.

Display device providing bi-directional voltage stabilization

A liquid crystal display includes a source driver, for generating a pixel data voltage, a gate driver, for generating a scanning signal voltage, and a plurality of pixel units. Each pixel unit includes a switch unit for delivering the pixel data voltage upon receiving the scanning signal voltage, a pixel electrode electrically coupled to the switch unit, a first electrode for supplying a first common voltage, a second electrode for supplying a second common voltage, a liquid crystal capacitor electrically coupled between the first electrode and the pixel electrode for driving liquid crystal layer in response to the pixel data voltage and the first common voltage, and a storage capacitor electrically coupled between the pixel electrode and the second electrode.

Liquid crystal display for reducing residual image phenomenon

The present invention relates to a pull-down control circuit and a shift register of using same. In one embodiment, the pull-down control circuit includes a release circuit and four transistors T, T, Tand Telectrically coupled to each other. The release circuit is adapted for causing the transistor Tto be turned on and off alternately, thereby substantially reducing the stress thereon, improving the reliability and prolonging the lifetime of the shift register.

Pull-down control circuit and shift register of using same

A shift register apparatus is provided. The pull-down unit of each of the shift registers in the shift register apparatus is controlled by itself, previous, and next two shift registers to enhance the ability of pull-down and voltage regulating. Therefore, the circuit structure of each of the shift registers does not need to be designed a large compensation capacitor therein to substantially restrain the coupling noise effect caused by the clock signal, and thus permitting that each of the shift registers can be collocated with a small compensation capacitor to enhance the output capability thereof.

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Hsin-Chu, Taiwan

Yi-Suei Liao