Realtek Semiconductor Inc.

Yi-Shu Chang

Wen-Chi Wang

Sen-Huang Tang

Ming-Jane Hsieh

Ming-Chun Chang

Chun-Hsing Hsieh

Hsu-Jung Tung

Chi-Kung Kuan

Chi-Wang Chai

Wei Li

Cheng-Hsin Chang

Cheng-Shun Liao

Wen-Che Wu

Rong Zhang

Wu-Jun Chen

Te-Ming Kuo

Shih-Yu Ku

Wei-min Zeng

Wen-Shiung Weng

Chu-Ting Su

Wen-Jui Lin

Jui-Cheng Huang

Chao-Cheng Lee

Yu-Pin Chou

Chao-Hsin Lu

Lien-Hsiang Sung

Hsien-Chun Chang

Tsung-Chi Lin

Pui-Kei Leong

Chia-Hao Hsiung

Zou-Ping Chen

Ming-Lih Lin

Shiu-Rong Tong

Chia-Pei Chang

Sheng-Kai Chen

Kuo-Lin Tai

Ting-Yang Chang

Seng-Huang Tang

Kuang-Hsi Hsieh

Jul-Cheng Huang

Chuting Su

Shi-Wei Chen

The present invention discloses an image decoding method. Error report information related to an error block in an N-th image frame generated according to an inter-frame coding technology is received by an image encoding apparatus at a time spot that the image decoding apparatus receives a corresponding block of an N+P−1-th image frame and an N+P-th image frame is encoded according to an inter-frame coding technology. Blocks in the N-th image frame before the occurrence of the error block are decoded according to the inter-frame coding technology. Motion vector information and residue information are set to be zero to decode the blocks from the error block to the N+P−1-th image frame according to the inter-frame coding technology. The motion vector information and the residue information of the inter-frame coding blocks in the N+P-th image frame are retrieved to decode the blocks therein according to the inter-frame coding technology.

Image decoding apparatus and method

The present invention discloses an image decoding method. Error report information related to an error block in an N-th image frame generated according to an inter-frame coding technology is received by an image encoding apparatus when the image decoding apparatus receives a block of an N+P−1-th image frame. The N+P-th image frame is encoded according to the inter-frame coding technology. Blocks in the N-th image frame before the error block are decoded according to the inter-frame coding technology. A panning motion vector of an N−1-th image frame serves as the motion vector information and the residue information is set to be zero to decode the blocks from the error block to the N+P−1-th image frame according to the inter-frame coding technology. The motion vector information and the residue information of the inter-frame coding blocks in the N+P-th image frame are retrieved to perform decoding according to the inter-frame coding technology.

A multimedia audio/video system includes a multimedia audio/video transmitting end and a multimedia audio/video receiving end. The multimedia audio/video transmitting end includes a multimedia data generator and a first data converter. The multimedia data generator is used to generate a multimedia data conforming to a first transmission protocol. The first data converter is used to convert the multimedia data conforming to the first transmission protocol into a multimedia data conforming to a second transmission protocol. The multimedia audio/video receiving end includes a second data converter which is used to convert the multimedia data conforming to the second transmission protocol into the multimedia data conforming to the first transmission protocol. The multimedia data conforming to the first transmission protocol is transmitted via multiple cables, while the multimedia data conforming to the second transmission protocol is transmitted via a single cable.

Multimedia audio/video system

A video processing system includes a main chip and a processing chip. The main chip receives first data. The processing chip is coupled to the main chip, and receives second data and to perform a video processing on at least one of the first data transmitted from the main chip and the second data, in order to drive a display panel. First video carried on the first data or second video on the second data has a first resolution, and the first resolution is at least 8K ultra high definition.

Video processing system and processing chip

The invention provides a digital television tuner having at least two branches that receive a radio frequency signal, wherein the radio frequency signal carries M channels (M is a positive integer). A target image data is generated in real time since at least one of the branches pre-extracts the image compression data of the next channel to be switched to.

Television tuner and method thereof

A controller and a method of updating parameters on the same. The controller includes an embedded non-volatile memory, a programming circuit, an embedded SRAM, a MCU (Micro Computer Unit), and a memory controller. The embedded non-volatile memory has a program code block for storing program codes to be executed by the MCU, and a data block for storing the parameters. The MCU writes the parameters into the data block of the flash memory through the memory controller, or reads data in the data block of the non-volatile memory through the memory controller. Because the controller does not need to employ an external EEPROM, the cost can be reduced and the speed for accessing the parameters can be increased.

Display controller having an embedded non-volatile memory divided into a program code block and a data block and method for updating parameters of the same

A system for programming at least a controller chip is disclosed. The system includes a programming apparatus and at least a programmable device mounted on the programming apparatus. The programming apparatus has at least a first connection interface and a micro-controller. The programmable device has the monitor controller chip mounted thereon and a second connection interface coupled between the first connection interface and the controller chip. The micro-controller controls the programming of the controller chip.

System and method for programming a display controller chip

An apparatus and method of automatic identification an external audio input/output device. The external device connected to an audio jack is identified as an audio output or input device, according to the impedance thereof. Furthermore, the present invention automatically selects the most suitable internal circuit to connect to the external device.

Apparatus for automatic identification of audio input/output device and method thereof

A video processing apparatus includes: a line-based data encoder for performing line-based data encoding on an input signal to generate a line-based data encoded signal; and a video signal controller coupled to the line-based data encoder for receiving a first video signal and the line-based data encoded signal, decoding the line-based data encoded signal to generate a second video signal, and choosing one of the first and second video signals to generate an output signal.

Video processing apparatus and method thereof

A video data displaying device is disclosed. The video data displaying device is used to drive a displayer according to a first display data set to display a first picture, the displaying device comprises a memory for storing the first display data set, and a display engine which is electrically connected to the memory for storing a part of the first display data set stored in the memory, wherein the display engine selects a specific display data set from the first display data set according to a display area of the displayer, and the display engine does not output the specific display data to the displayer.

Video data processing method and apparatus for processing video data

An image scaling method for calculating a pixel value of a target pixel within a scaled image block is disclosed. The method includes selecting a plurality of reference pixels from the image block, wherein each reference pixel has a pixel value and corresponds to a transparency parameter; respectively setting a corresponding weight value for each reference pixel; adjusting the weight values according to the transparency parameters of the reference pixels; and blending the pixel values of the reference pixels to generate the pixel value of the target pixel according to the adjusted weight values of the reference pixels.

Method and apparatus for scaling image block

A video processing method utilized in a video data processing device for processing video data is disclosed. The video data includes at least a first video data set, and the video data processing device has a memory and a video decoder. The method includes utilizing the video decoder to decode the video data for generating a display data set, driving the video decoder to select a specific video data set from the first video data set wherein the display data set does not have display data corresponding to the specific video data set, and utilizing the memory to store the display data.

A VBI receiver and method is disclosed. The receiver includes an over-sampling circuit, a transition detector, a data selector, and a data output device. The over-sampling circuit is for over-sampling VBI data and outputting and over-sampled signal. The transition detector is for detecting the transition of the over-sampled signal and outputting a transition signal representing the transition position. The data selector is for recording the transition signal and outputting a position signal according to the transition signal and at least a previous transition signal. The data output device outputs digital output data from the over-sampled signal according to the position signal.

Data receiving apparatus and method in a VBI receiver

A data recovery device. The device adjusts a digital signal according to a pulse signal output by a phase-locked loop circuit. The sampling circuit samples each bit of the digital signal five times to generate a first sampled signal. The data delay buffer decides a sampling range of the first sampled signal and outputs a second sampled signal. The sampling range selector picks a part of bits of the second sampled signal and outputs output data. The weighted detecting module outputs a phase shifting signal responding to the output data. The first loop filter outputs a first adjusting signal. The first sampling window module outputs a phase selecting signal. The second loop filter outputs the recovery signal and a second adjusting signal. The second sampling window module outputs the first phase checking signal and the second phase checking signal. The phase picking module outputs the output data.

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Tainan, Taiwan

Yi-Shu Chang