Intel Corporation

Cadence Design Systems, Inc.

Visualon, Inc.

Yi Qian

Vincent J Zimmer

Michael A Rothman

Hua Zhou

Fujin Huang

Gang Wang

Hui Calvin Yang

Jianhui Li

Pinhong Chen

Chin-Yee Lin

Xueliang Zhong

Dongzi Liu

Junwei Chen

Yanhui Wang

WenHsing Tsai

Jian Ping Jane Chen

Huifeng Gu

Hanyue Yang

Wanshuan Liu

Systems and methods are provided in example embodiments for performing binary translation. A binary translation system converts, by a translator module, source instructions to target instructions. The binary translation system identifies a condition code block in the source instructions, where the condition code block includes a plurality of condition bits. In response to identifying the condition code block, the binary translation system provides an optimizer module to convert the condition code block. Then, the binary translation system performs a pre-execution on the condition code block to resolve the plurality of condition bits in the condition code block.

Methods and systems for performing a binary translation

A system for video decoding includes an interface, a set of cores, an allocator, and a load metric measurer. The interface is to receive a set of encoded video frames. The set of cores is to process data. The allocator is to determine an assignment of the set of video decoding modules to the set of cores. The load metric measurer to measure load metrics for each module of the set of modules during decoding of the set of encoded video frames. The allocator is to determine a reassignment of the set of modules to the set of cores based at least in part on the load metrics.

Self-adaptive load balance optimization for multicore parallel processing of video data

A system, method, and computer program product for automatically optimizing circuit designs. A graphical user interface based environment allows arbitrary selection of a circuit design region to be optimized based on physical layout, without regard for logical hierarchy. Embodiments analyze circuit paths crossing optimization region boundaries and replace externally connected circuitry with an interface logic model describing such circuitry from the optimization region boundary to a first register occurrence. A reduced netlist spans the regional circuitry and the modeled external circuitry. Embodiments optimize the reduced netlist under design constraints applicable to the full circuit design. Changes to the original circuit design made by the optimization are tangibly saved as engineering change orders. The optimization process may be applied to other regions, including via parallel execution by multiple processors. Conventional design bottlenecks may be bypassed for greatly improved quality of results and reduced turnaround time.

Reverse interface logic model for optimizing physical hierarchy under full chip constraint

In a computing system, sharing a physical NIC device among multiple virtual machines may be implemented by a customer virtual machine by receiving, by a virtual network interface card (NIC) driver of a customer operating system (OS) running in the customer virtual machine on a computing system, a customer OS request packet for transmission by a physical NIC driver over a network coupled to the computing system, and copying at least a portion of the customer OS request packet into a free block of shared memory of the computing system and appending the block to a transmission queue in the shared memory. Next, a service virtual machine may support the implementation by fetching the block from the transmission queue by a virtual NIC driver of a service OS running in a service virtual machine and packaging the portion into a service OS request packet, passing the service OS request packet to a service OS network stack component of the service OS, routing the service OS request packet, by a bridge driver of the service OS network stack component, to the physical NIC driver, and sending the service OS request packet over the network by the physical NIC driver.

Method for network interface sharing among multiple virtual machines

In a computing system having a processor package, an operating system, and a physical I/O device, a partial virtual machine is provided to instantiate a virtual I/O device corresponding to the physical I/O device, the virtual I/O device having a virtual I/O controller. The partial virtual machine includes an I/O port trap to capture an I/O request to the virtual I/O device by the operating system; an I/O controller emulator coupled to the I/O port trap to handle an I/O control request to the virtual I/O controller, when the I/O request comprises an I/O control request; an I/O device emulator coupled to the I/O port trap component to handle an I/O access request to communicate with the virtual I/O device, when the I/O request comprises an I/O access request; and a device driver coupled to the I/O controller emulator and the I/O device emulator to communicate with the physical I/O device based at least in part on the I/O control request and the I/O access request. The partial virtual machine executes within a secure enclave session within the processor package, improving security of I/O transactions by preventing access to the partial virtual machine by the operating system.

Uniform storage device access using partial virtual machine executing within a secure enclave session

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Shanghai, China

Yi Qian