United Microelectronics Corp.

Yi-Po Lin

Jiunn-Hsiung Liao

Chieh-Te Chen

Shang-Yuan Tsai

Feng-Yi Chang

Shui-Yen Lu

Li-Chiang Chen

Ching-Pin Hsu

Chih-Wen Feng

Shih-Fang Tzou

Feng-Yih Chang

A method for fabricating a semiconductor device, wherein the method comprises steps as follows: A dummy gate with a poly-silicon gate electrode and a passive device having a poly-silicon element layer are firstly provided. A hard mask layer is then formed on the dummy gate and the passive device. Next, a first etching process is performed to remove a portion of the hard mask layer to expose a portion of the poly-silicon element layer. Subsequently, an inner layer dielectric (ILD) is formed on the dummy gate and the poly-silicon element layer, and the ILD is flattened by using the hard mask layer as a polishing stop layer. Thereafter, a second etching process is performed to remove the poly-silicon gate electrode, and a metal gate electrode is formed on the location where the poly-silicon gate electrode was initially disposed.

Method for fabricating semiconductor device to integrate transistor with passive device

A manufacturing method of a semiconductor device is disclosed in the present invention. First, at least one gate structure and plurality of source/drain regions on a substrate are formed, a dielectric layer is then formed on the substrate, a first contact hole and a second contact hole are formed in the dielectric layer, respectively on the gate structure and the source/drain region, and a third contact hole is formed in the dielectric layer, wherein the third contact hole overlaps the first contact hole and the second contact hole.

Manufacturing method of semiconductor device

A semiconductor structure includes a substrate, a resist layer, a dielectric material, two U-shaped metal layers and two metals. The substrate has an isolation structure. The resist layer is located on the isolation structure. The dielectric material is located on the resist layer. Two U-shaped metal layers are located at the two sides of the dielectric material and on the resist layer. Two metals are respectively located on the two U-shaped metal layers. This way a semiconductor process for forming said semiconductor structure is provided.

Semiconductor process

Semiconductor structure and process thereof

In an exemplary method for forming contact holes, a substrate overlaid with an etching stop layer and an interlayer dielectric layer in that order is firstly provided. A first etching process then is performed to form at least a first contact opening in the interlayer dielectric layer. A first carbon-containing dielectric layer subsequently is formed overlying the interlayer dielectric layer and filling into the first contact opening. After that, a first anti-reflective layer and a first patterned photo resist layer are sequentially formed in that order overlying the carbon-containing dielectric layer. Next, a second etching process is performed by using the first patterned photo resist layer as an etching mask to form at least a second contact opening in the interlayer dielectric layer.

Method for forming contact holes

A method for forming a dielectric layer free of voids is disclosed. First, a substrate, a first stressed layer including a recess, a second stressed layer disposed on the first stressed layer and covering the recess and a patterned photoresist embedded in the recess are provided. Second, a first etching step is performed to totally remove the photoresist so that the remaining second stressed layer forms at least one protrusion adjacent to the recess. Then, a trimming photoresist is formed without exposure to fill the recess and to cover the protrusion. Later, a trimming etching step is performed to eliminate the protrusion and to collaterally remove the trimming photoresist.

Method for forming void-free dielectric layer

A semiconductor device comprises a metal gate electrode, a passive device and a hard mask layer. The passive device has a poly-silicon element layer. The hard mask layer is disposed on the metal gate electrode and the passive electrode and has a first opening and a second opening substantially coplanar with each other, wherein the metal gate electrode and the poly-silicon element layer are respectively exposed via the first opening and the second opening; and there is a distance between the first opening and the metal gate electrode substantially less than the distance between the second opening and the poly-silicon element layer.

Semiconductor device and fabrication method thereof

A method for fabricating an aperture is disclosed. The method includes the steps of: forming a hard mask containing carbon on a surface of a semiconductor substrate; and using a non-oxygen element containing gas to perform a first etching process for forming a first aperture in the hard mask.

Method for fabricating an aperture

A method for fabricating MOS transistor includes the steps of: overlapping a second stress layer on an etching stop layer and a first stress layer at a boundary region of the substrate; forming a dielectric layer on the first stress layer and the second stress layer; performing a first etching process to partially remove the dielectric layer for exposing a portion of the second stress layer at the boundary region; performing a second etching process to partially remove the exposed portion of the second stress layer for exposing the etching stop layer; performing a third etching process to partially remove the exposed portion of the etching stop layer for exposing the first stress layer at the boundary region; and performing a fourth etching process partially remove the exposed portion of the first stress layer.

Growing community of inventors

Tainan, Taiwan

Yi-Po Lin