Industrial Technology Research Institute

Tsinghua University

Yi-Ping You

Jeng Kuen Lee

Kuo Yu Chuang

Chung-Hsien Wu

Chi-Lung Wang

Jenq-Kuen Lee

Yung-Chia Lin

Chung-Wen Huang

Chung Wen Huang

The invention relates to a multi-thread power gating control design, setting idle components into a sleep mode to reduce power consumption due to current leakage. Based on compiler techniques, the invention arranges predicted-power-gating instructions into every thread of a may-happen-in-parallel region. A predicted-power-on instruction determines whether the corresponding component has been powered on, and powers on the component when it has not been powered on yet. A predicted-power-off instruction determines whether the component is required in the rest of the may-happen-in-parallel region, and powers off the component when it is required later.

Multi-thread power-gating control design

A system chip includes a plurality of processing elements for performing primary computations of a plurality of tasks, a plurality of non-processing elements for controlling flow of data associated with the tasks among the processing elements, and a main controller including a scheduler, a resource allocation module, and a power management module. The scheduler assigns the tasks on the processing and non-processing elements with reference to time parameters of the processing and non-processing elements. The resource allocation module controls operations of the processing and non-processing elements with reference to task assignments determined by the scheduler. The power management module performs dynamic voltage management upon the processing and non-processing elements according to the scheduled tasks.

Task scheduling method for low power dissipation in a system chip

A method of power-gating instruction scheduling for leakage power reduction comprises receiving a program, generating a control-flow graph dividing the program into a plurality of blocks, analyzing utilization of power-gated components of a processor executing the program, generating the first power-gating instruction placement comprising power-off instructions and power-on instructions to shut down the inactive power-gated components, generating the second power-gating instruction placement by merging the power-off instructions as one compound power-off instruction and merging the power-on instructions as one compound power-on instruction, and inserting power-gating instructions into the program in accordance with the second power-gating instruction placement.

Power-gating instruction scheduling for power leakage reduction

Growing community of inventors

Taichung County, Taiwan

Yi-Ping You