Synopsys, Inc.

Synopsys Taiwan Co., Ltd.

Yi-Peng Weng

Hung-Ming Chen

Tung-Chieh Chen

A computer implemented method for forming an integrated circuit (IC) layout is presented. The method includes forming a constraint tree when a computer is invoked to receive a first layout of the IC and generating a second layout of the IC in accordance with the constraint tree.

Method of fast analog layout migration

A method of fast analog layout migration from an original layout is disclosed. Various placement constraints, including topology, matching and symmetry are extracted from the schematic or netlist as well as the original layout. In addition, relative placement patterns are extracted from the original layout for matching and symmetry constraints. A constraint hierarchy tree can be built according to the constraints, and relative placement patterns are attached accordingly. By using the constraint hierarchy tree, multiple new placement results are efficiently explored that preserve the relative placement patterns for matching and symmetry constraints.

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Taipei, Taiwan

Yi-Peng Weng