Gpower Semiconductor, Inc.

Dynax Semiconductor, Inc.

Yi Pei

Naiqian Zhang

Yuan Li

Feihang Liu

Qiang Liu

Xingxing Wu

Junfeng Wu

Xi Song

Chuanjia Wu

Chenggong Yin

Shiqiang Li

Hui Zhang

Guangmin Deng

Jian Liu

Mengjie Zhou

Hongtu Qian

Mao Hu

Guochun Kang

Xin Jin

Linlin Sun

Disclosed are an epitaxial structure of a semiconductor device, a manufacturing method, and a semiconductor device. The epitaxial structure includes a substrate and a semiconductor layer; the semiconductor layer includes a buffer layer; the buffer layer includes a first buffer subsection and a second buffer subsection which are connected to each other and arranged along a direction from a source preset region to a drain preset region, and a vertical projection on the substrate of the first buffer subsection overlaps with a vertical projection on the substrate of the source preset region, and a vertical projection on the substrate of the second buffer subsection overlaps with a vertical projection on the substrate of each of the gate preset region and the drain preset region; an ion implant concentration in the second buffer subsection is greater than or equal to an ion implant concentration in the first buffer subsection.

Epitaxial structure of semiconductor device and manufacturing method thereof and semiconductor device

Embodiments of the present disclosure provide an epitaxial structure of a semiconductor device and a method of manufacturing the same. The epitaxial structure includes a substrate, and an epitaxial layer located on a side of the substrate, the epitaxial layer including a nucleation layer located on a side of the substrate and a buffer layer located on a side of the nucleation layer away from the substrate, wherein a thickness of the buffer layer is inversely proportional to a thickness of the nucleation layer.

Epitaxial structure of semiconductor device and method of manufacturing the same

The present disclosure discloses a dual output energy conversion device, modulation method, and power supply device which can enhance the bus voltage boosting capability of the conversion device by using a first electric energy storage module, so that it can be used in a wider input voltage range. A first conversion output circuit and a second conversion output circuit are set, and voltage stress of all switching tubes is reduced to half of the direct current bus voltage, which can greatly reduce the system EMI of the conversion device in high-frequency applications, and improve the power conversion efficiency of the device. The dual output energy conversion device only needs to realize the control of one-stage power conversion, and has a simple control structure.

Dual output energy conversion device, modulation method and power supply device

The present disclosure discloses a semiconductor device and a method for preparing the same. The semiconductor device includes a substrate, a doped epitaxial layer located on one side of the substrate, a channel layer located on one side of the doped epitaxial layer away from the substrate, a potential barrier layer located on one side of the channel layer away from the doped epitaxial layer, and a first electrode and a second electrode located on one side of the potential barrier layer away from the channel layer, wherein the first electrode penetrates the potential barrier layer, the channel layer and part of the doped epitaxial layer, the first electrode forms a Schottky contact with the channel layer, and a resistance of the part of the doped epitaxial layer in contact with the first electrode is greater than a resistance of the channel layer.

Semiconductor device comprising a doped epitaxial layer and method of manufacturing the same

The present disclosure discloses a semiconductor device, a method of manufacturing the same, and a semiconductor package structure. The semiconductor device including a substrate, a multilayer semiconductor layer located on one side of the substrate, in which a Two-Dimensional Electron Gas is formed, a first source, a first gate and a first drain located on one side of the multilayer semiconductor layer and located within an active region of the multilayer semiconductor layer, the first gate being located between the first source and the first drain, and a back surface gate contact electrode located on one side of the substrate away from the multilayer semiconductor layer, wherein the first gate is electrically connected to the back surface gate contact electrode. A signal is provided from the back surface of the semiconductor device to the first gate, to reduce the parasitic inductance and parasitic resistance caused by the device during the packaging process.

Semiconductor device comprising a drain back contact electrode, method of manufacturing the same, and semiconductor package structure

Embodiments of the disclosure provide a semiconductor device, a semiconductor chip and a method of manufacturing a semiconductor device, wherein the semiconductor device, includes a substrate, a semiconductor layer formed on the substrate, a plurality of gates, drains, and a plurality of sources formed on a side of the semiconductor layer away from the substrate, the gates located between the sources and the drains, and the gates, sources, and drains located in an active region of the semiconductor device, wherein a gate pitch is formed between any two adjacent gates, the formed respective gate pitches include at least two unequal gate pitches, the maximum gate pitch of the respective gate pitches is within a first preset range determined according to a pitch of two gates at the two outermost ends in the semiconductor device in the gate length direction and a total number of gates of the semiconductor device.

Semiconductor device, semiconductor chip and method of manufacturing semiconductor device

The present disclosure provides a semiconductor device and a method of manufacturing the same, and relates to the field of semiconductor devices. The semiconductor device includes an active region, a test region and a passive region located outside the active region and the test region, wherein a standard device is formed in the active region, and a test device for testing performance parameters of the standard device is formed in the test region.

Semiconductor device and method of manufacturing the same

A semiconductor device comprises: a substrate; a semiconductor layer formed on the substrate; a source electrode, a drain electrode and a gate electrode between the source electrode and the drain electrode formed on the semiconductor layer; and a source field plate formed on the semiconductor layer. The source field plate sequentially comprises: a start portion electrically connected to the source electrode; a first intermediate portion spaced apart from the semiconductor layer with air therebetween; a second intermediate portion disposed between the gate electrode and the drain electrode in a horizontal direction, without air between the second intermediate portion and the semiconductor layer; and an end portion spaced apart from the semiconductor layer with air therebetween.

Semiconductor device having source field plate and method of manufacturing the same

The present disclosure provides a semiconductor device and a method for manufacturing the same. A semiconductor device according to a performing mode includes a substrate, a semiconductor layer located on one side of the substrate, a source and a drain located on one side of the semiconductor layer away from the substrate, and a gate located between the source and the drain, and an isolation structure disposed on one side of the semiconductor layer away from the substrate, one end of the isolation structure being disposed at a side close to the source, and the other end being disposed at a side close to the drain and in direct contact with the surface layer of the semiconductor device, the isolation structure covering the gate or a part of the gate, the isolation structure being an integrally formed structure and forming a chamber with the semiconductor layer.

Semiconductor device and method for manufacturing the same

The present disclosure provides a semiconductor device and a manufacturing method thereof. The semiconductor device includes a semiconductor layer, a source and a drain located on one side of the semiconductor layer, a blocking layer located on one side of the semiconductor layer, the blocking layer including silicide, wherein the distance between an interface at one side of the blocking layer close to the semiconductor layer and the semiconductor layer is equal to or more than 10 nm, and a gate located between the source and the drain, the gate penetrating through the blocking layer, the gate including a first conductive layer and a second conductive layer, the first conductive layer being close to the semiconductor layer, the second conductive layer being located on one side of the first conductive layer away from the semiconductor layer, and the first conductive layer including nickel.

The present disclosure provides a schottky barrier rectifier, comprising: a communication layer; a drift layer provided on a side of the communication layer and forming a heterojunction structure together with the communication layer; anode metal provided on a side of the drift layer away from the communication layer; and cathode metal provided on a side of the communication layer away from the drift layer. The drift layer is provided with a first area, which extends in a direction of thickness thereof, between a surface of the drift layer away from the communication layer and a surface thereof close to the communication layer, the first are a containing a first metal element and the content of the first metal element in the first area changing in the direction of thickness. The rectifier of the present disclosure uses polarized charges formed by a heterojunction, and thus the breakdown voltage of devices may be improved.

Schottky barrier rectifier

A field plate power device comprises: a substrate; a multilayer semiconductor layer disposed on the substrate; a source electrode, a drain electrode, and a gate electrode located between the source electrode and the drain electrode disposed on the multilayer semiconductor layer; a dielectric layer disposed on the gate electrode, a part of the multilayer semiconductor layer between the gate electrode and the source electrode and another part of the multilayer semiconductor layer between the gate electrode and the drain electrode; a groove disposed in a part of the dielectric layer between the gate electrode and the drain electrode; and a field plate disposed on the groove. The field plate comprises a first portion away from the gate electrode in a horizontal direction, and the first portion has an overall upward tilted shape in the horizontal direction away from the gate electrode.

Field plate power device and method of manufacturing the same

A semiconductor device comprises an active region and a passive region located outside the active region. The active region comprises a plurality of active region units. At least one pair of adjacent active region units do not completely overlap in a length direction of the semiconductor device.

A semiconductor device comprises: a substrate; a multi-layer semiconductor layer located on the substrate, the multi-layer semiconductor layer being divided into an active area and a passive area outside the active area; a gate electrode, a source electrode and a drain electrode all located on the multi-layer semiconductor layer and within the active area; and a heat dissipation layer covering at least one portion of the active area and containing a heat dissipation material. In embodiments of the present invention, a heat dissipation layer covering at least one portion of the active area is provided in the semiconductor device. The arrangement of the heat dissipation layer adds a heat dissipation approach for the semiconductor device in the planar direction, thus the heat dissipation effect of the semiconductor device is improved.

Semiconductor device

The embodiments of the present invention disclose a high electron mobility transistor, comprising: a substrate; a channel layer located on the substrate; a barrier layer located on the channel layer; a source electrode, a drain electrode, and a schottky gate electrode located between the source electrode and the drain electrode, all located on the barrier layer; and at least one semiconductor field ring located on the barrier layer and between the schottky gate electrode and the drain electrode. In the embodiments of the present invention, a concentration of two-dimensional electron gas at an interface between a barrier layer and a channel layer can be adjusted. Therefore, the concentration effect of the electric field at an edge of a gate is effectively improved, and the breakdown voltage of high electron mobility transistors is increased.

Growing community of inventors

Suzhou, China

Yi Pei