International Business Machines Corporation

Yi-Ming Ku

Thang Q Nguyen

John Steven Langford

Michael Youhour Lim

Joel Gerald Goodwin

Wallace G Tuten

A computer system including a central processing unit and a system memory accessible to the central processing unit via a host bus. A primary non-volatile storage element and a backup non-volatile storage element are incorporated into the system's motherboard. The primary non-volatile storage element contains the system's boot code that is executed following a reset or power on event. The backup non-volatile storage element contains a restoration sequence that is suitable for reprogramming a first portion of the boot code in the primary non-volatile storage element. A jumper block on the motherboard determines which of the non-volatile storage elements is initially addressed following a power on event. Preferably, the first portion of the boot code comprises the system's boot block or gold code and includes a sequence for downloading and reprogramming remaining portions of the boot code. The primary non-volatile storage element is preferably implemented as a multiple sector flash memory device. In one embodiment, the gold code is stored in a first sector of the flash module and the update code is stored in remaining sectors.

Gold code backup for corrupt boot code recovery

A method of configuring a data communications system, by changing a default communications address of a logic component to a first assigned address, and connecting the logic component to a communications bus automatically in response to the address change. The logic component may include a multiplexer having an input connected to a first communications bus, and several outputs, some of the outputs being connected to input/output (I/O) devices, and at least one of the outputs being connected to a second communications bus. The latter output is disabled when the logic component has the default communications address; the logic component is connected to the second communications bus by enabling the output of the multiplexer. The invention is particularly adapted for use with a computer system, wherein a service processor having an I C port is connected to the first communications bus, and the service processor communicates with the logic component using an I C bus protocol to send data across the first communications bus to an input/output expander of the second logic component.

Configurable I/O expander addressing for I/O drawers in a multi-drawer rack server system

A driver circuit for use in a system that includes first, second, and possibly more power supplies. The driver circuit includes a first line driver with an output connected to a first receiver circuit and a second line driver with an output connected to a second receiver circuit. A first output enable control circuit is connected to an output enable of the first line driver. The first power supply provides an input to the output enable control circuit such that the state of the first line driver output enable is a function of the first power supply. In one embodiment, the first receiver circuit is powered by the first power supply and the second receiver circuit is powered by the second power supply. In one embodiment, the first power supply is the Vcc power supply of the system and the second power supply is the Vccsb (vcc standby) power supply of the system. In the preferred embodiment, the first output enable assumes a high impedance state when the first power supply is off and the second output enable is independent of the first power supply.

Automated line driver control circuit for power managed system

A shared peripheral controller including a primary bus interface, a primary bus first register, a shared bus interface, and a control unit. The primary bus interface is adapted to receive an operation via a primary bus, such as an ISA bus, from a first processor, such as a PCI-to-ISA bus bridge. The shared bus interface is adapted to communicate with a first shared peripheral, such as a real time clock, via a shared bus. The control unit is coupled to the primary bus interface and configured to detect a first segment of a first operation issued by the first processor to the first shared peripheral. The control unit is further configured to buffer the first segment in the primary bus first register until the control unit detects a second segment of the first operation whereupon the control unit is configured to issue the first and second segments of the first operation to the first shared peripheral in consecutive cycles of the shared bus. In the preferred embodiment, the controller further includes a secondary bus first register and a secondary bus interface that is adapted to receive an operation via a secondary bus, such as a 68000 bus, from a second processor, such as a service processor. In this embodiment, the control unit is coupled to the secondary bus interface and configured to detect a first segment of a second operation that is issued by the second processor and further adapted to buffer the second operation's first segment in the secondary bus first register until the control unit detects a second segment of the second operation whereupon the second operation's second segment, the control unit issues the second operation's first and second segments to the first shared peripheral in consecutive cycles of the shared bus.

Shared peripheral controller

A serial/parallel interface for interfacing the serial port of a microcontroller with parallel bus devices, and a protocol for communicating with the same. The interface operates to maximize through-put with minimum handshaking by incorporating logic within the interface itself to control data flow. A row/column count state machine in the interface accumulates serial clock pulses from the microcontroller and controls the latching of parallel output data. A read/write state machine accumulates addresses and controls the read/write operation in response to a command sent by the microcontroller in the serial data stream. The read/write state machine accumulates addresses in response to an interface clock derived from the serial clock from the microcontroller.

Handshake minimizing serial-to-parallel interface with shift register

A serial/parallel interface for interfacing the serial port of a microcontroller with parallel bus devices, and a protocol for communicating with the same. The interface operates to maximize through-put with minimum handshaking. When the bus device is a nonvolatile memory containing the operating software of the microcontroller system, the interface provides for dynamic updating of the operating program. It also relieves the constraints imposed on the number of bus devices accessible to the microcontroller system because of the limited number of I/O pins available on the microcontroller.

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Austin, TX, United States of America

Yi-Ming Ku