United Microelectronics Corp.

United Microelectronics Corps.

Yi-Min Jen

Tse-Yi Lu

Kuo-Yuh Yang

Yu-Chih Chuang

Yu-Hong Huang

Yu-Ju Yang

Kuan-Te Pai

Li-Wu Tsao

Ya-Ling Hung

A method for increasing tolerance of contact extension alignment in a capacitor over a bit line of a dynamic random access memory is disclosed. Firstly, a substrate having a gate, a bit line and a source/drain region is provided and a insulating layer is formed on the substrate. Then, a dielectric layer is deposited on the insulating layer. Moreover, a contact hole is formed by defining and etching the dielectric layer and the insulating layer to expose a portion of the source/drain region. Furthermore, a conductive layer is deposited on the dielectric layer and the contact hole, wherein the etching selectivity ratio of the conductive layer is near the etching selectivity ratio of the dielectric layer. Finally, an electrode of the capacitor is formed by defining and etching the conductive layer, whereby the dielectric layer protects the portion of the electrode that is beneath the dielectric layer from being etched when misalignment occurs.

Method for increasing tolerance of contact extension alignment in COB DRAM

A static random access memory manufacturing method. A substrate having a gate oxide layer and a first conducting layer is defined to form a buried contact window opening. A second conducting layer is formed upon the substrate with a recess structure at the region of the buried contact opening. A buried contact window is formed in the substrate under the buried contact window opening. A protective layer is formed upon the substrate and fills the recess. A portion of the protective layer is removed, and a patterned photoresist layer is formed upon the substrate. Using the photoresist as a mask, the first and second conducting layer are etched to form a gate electrode and an interconnect. The patterned photoresist layer is removed. The protective layer can be removed or retained. An implantation procedure is performed, thereby forming a source/drain, thereby connecting the source/drain and the contact window.

Static random access memory manufacturing method

A method for manufacturing trench isolation, comprising firstly, defining a trench isolation over the substrate by photolithography and etching technique. Beside, by way of a spacer fabricating process to form a spacer around each of the two sides of the trench isolation. Therefore, a sharp corner in the crossing region between the trench isolation and an active area adjacent thereto in the substrate is smoothed, and the process window for a sequential gate polysilicon etching is improved, as well as the opportunity to leave polysilicon residue in the corner is eliminated. The short circuit between polysilicon gates is also avoided.

Method for manufacturing trench isolation

A method of fabricating a buried contact in a static random access memory. A gate oxide layer, a first conducting layer and a masking layer are formed sequentially on a substrate. A buried contact opening is formed inside the gate oxide layer, the first conducting layer and the masking layer, which opening exposes a part of the substrate. An epitaxial layer is formed inside the buried contact opening, which epitaxial layer fills up the buried contact opening. After the masking layer is removed, a second conducting layer is formed above the substrate. A buried contact is formed in the substrate that is below the epitaxial layer. The gate oxide layer, the first conducting layer, the epitaxial layer and second conducting layer are patterned to expose a part of the substrate and a part of the buried contact. A source/drain is formed in the substrate and a part of the source/drain is mixed with a part of the buried contact.

Method of fabricating a static random access memory

A method for manufacturing a trench isolation in a semiconductor device is disclosed, wherein a silicon nitride layer used as an anti-diffusion layer mask that defines an isolation region on a silicon substrate and a thermal oxidation process that is performed on active regions are previously used. A silicon substrate having a first pad oxide layer and a first silicon nitride layer formed thereon is first provided. Then the first pad oxide layer and the first silicon nitride layer are patterned to form an anti-diffusion layer mask and to expose an active region of the silicon substrate. Next the silicon substrate is oxidized to form a first silicon dioxide layer, wherein lateral oxidation on the active region of the silicon substrate underneath the first pad oxide layer and the first silicon nitride layer provides an edge of the first silicon dioxide layer in the shape of a bird's beak. Moreover, the first silicon nitride layer, the first pad oxide layer and the first silicon dioxide layer are removed to expose the silicon substrate. Furthermore, a second pad oxide layer is formed on the substrate and a second silicon nitride layer is deposited thereon. Finally, an isolation trench of the invention can be formed by using a conventional method.

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Pan-Chiao, Taiwan

Yi-Min Jen