Taiwan Semiconductor Manufacturing Comp. Ltd.

Realtek Semiconductor Inc.

Yi-Lun Chen

Li-Te S Lin

Chun-Hsiung Lin

Chao-Hsien Huang

Pinyen Lin

Han-Yu Lin

Fang-Wei Lee

Bau-Ming Wang

Tze-Chung Lin

Jung-Hao Chang

Yi-Chen Lo

Jin-Ru Chen

Hsiao-Wen Chung

Fo-Ju Lin

Kenichi Sano

Shan-Yu Huang

Huang-Sheng Lin

Mao-Lin Huang

Yi-Ruei Jhan

Chun-Feng Liu

A semiconductor structure includes first and second inner seal rings each having a first section and a second section substantially perpendicular to the first section. The semiconductor structure further includes an outer seal ring. The outer seal ring has a third section, and a fourth section, and a fifth section. The semiconductor structure further includes dummy patterns substantially uniformly distributed in each of regions between the first inner seal ring and the outer seal ring and between the second inner seal ring and the outer seal ring.

Dummy patterns in redundant region of double seal ring

A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material is received. A plurality of first main etches are performed to the semiconductor structure for a plurality of first durations under the first etching chemistry. A plurality of pumping operations are performed for a plurality of pumping durations, each of the pumping operations being prior to each of the first main etches. Each of the first durations is in a range of from about 1 second to about 2.5 seconds.

Technique for semiconductor manufacturing

A method includes forming a gate stack over a semiconductor region, and forming a first gate spacer on a sidewall of the gate stack. The first gate spacer includes an inner sidewall spacer, and a dummy spacer portion on an outer side of the inner sidewall spacer. The method further includes removing the dummy spacer portion to form a trench, and forming a dielectric layer to seal a portion of the trench as an air gap. The air gap and the inner sidewall spacer in combination form a second gate spacer. A source/drain region is formed to have a portion on an outer side of the second gate spacer.

Air spacers in transistors and methods forming same

A method includes forming a semiconductor fin over a substrate; forming a gate structure over the semiconductor fin; forming a helmet layer lining the gate structure and the semiconductor fin; etching the helmet layer to remove portions of the helmet layer from opposite sidewalls of the gate structure, wherein the remaining helmet layer comprises a first remaining portion on a top surface of the gate structure and a second remaining portion on a top surface of the semiconductor fin; forming a spacer layer covering the gate structure, wherein the spacer layer is in contact with the first remaining portion and the second remaining portion of the remaining helmet layer; etching the spacer layer and the remaining helmet layer to form gate spacers, wherein each of the gate spacers has a stepped sidewall; and forming source/drain epitaxy structures on opposite sides of the gate structure.

Method of manufacturing gate spacers with stepped sidewalls by removing vertical portions of a helmet layer

The present disclosure relates to a semiconductor device that includes a first terminal formed on a fin region and having a first spacer. The semiconductor device further includes a second terminal having a hard mask and a second spacer opposing the first spacer. The hard mask and the second spacer are formed using different materials. The semiconductor device also includes a seal layer formed between first and second spacers of the first and second terminals, respectively. The semiconductor device further includes an air gap surrounded by the seal layer, the fin region, and the first and second spacers.

Silicon carbide oxide hard mask for reducing dishing effects

A semiconductor structure that includes two circuit regions; two inner seal rings, each of the two inner seal rings surrounding one of the two circuit regions; an outer seal ring surrounding the two inner seal rings, wherein each of the inner seal rings and the outer seal ring has a substantially rectangular periphery with four interior corner seal ring structures; four first redundant regions between the two inner seal rings and the outer seal ring, each of the four first redundant regions being a substantially trapezoidal shape; and first dummy patterns substantially uniformly distributed in the four first redundant regions.

A semiconductor device includes a substrate, an isolation structure, a first gate structure, a first gate spacer, and an epitaxy structure. The substrate has a semiconductor fin. The isolation structure is over the substrate and laterally surrounds the semiconductor fin. The first gate structure is over the substrate and crosses the semiconductor fin. The first gate spacer extends along a sidewall of the first gate structure, in which the first gate spacer has a stepped sidewall distal to the first gate structure. The epitaxy structure is over the semiconductor fin, in which the epitaxy structure is in contact with the stepped sidewall of the first gate spacer.

Fin semiconductor device having a stepped gate spacer sidewall

A technique for semiconductor manufacturing is provided. The technique includes the operations as follows. A semiconductor structure having a first material and a second material is revived. The first material has a first incubation time to a first etching chemistry. The second material has a second incubation time to the first etching chemistry. The first incubation time is shorter than the second incubation time. A first main etch to the semiconductor structure for a first duration by the first etching chemistry is performed. The first duration is greater than the first incubation time and shorter than the second incubation time.

In some embodiments, a method is provided. Dummy gate stacks are formed over a semiconductor substrate. An interlayer dielectric (ILD) layer is formed over the dummy gate stacks. A first portion of the ILD layer over top surfaces of the dummy gate stacks is removed, such that a second portion of the ILD layer remains between the dummy gate stacks. The dummy gate stacks are replaced with metal gate stacks. Neutral NFradicals into the water are applied to etch the ILD layer.

Method for forming semiconductor device

A method includes forming a semiconductor fin over a substrate; forming a helmet stack on a top surface of the semiconductor fin; forming a spacer layer over the helmet stack and on opposite sidewalls of the semiconductor fin; and etching the helmet layer and the spacer layer to expose the top surface and the sidewalls of the semiconductor fin.

Method of manufacturing a protective stack on a semiconductor fin

A bandwidth control method is adapted for use in a network device having a system clock. The network device has a register for storing a transmittable data amount to control bandwidth. The method includes: calculating a number of elapsed periods of the system clock so as to change a counting value every predetermined time interval, the counting value being cyclic within a specific range; adjusting the transmittable data amount in the register by a first unit amount when the counting value reaches a first count value; and adjusting the transmittable data amount in the register by a second unit amount after adjusting the transmittable data amount by the first unit amount and elapse of the predetermined time interval and when the counting value corresponds to a second count value. The first count value is different from the second count value, and the first unit amount is different from the second unit amount.

Growing community of inventors

Taichung, Taiwan

Yi-Lun Chen