Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

University of Massachusetts

Shanghai Huahong Grace Semiconductor Manufacturing Corporation

Micron Technology Incorporated

Shanghai Sensetime Intelligent Technology Co., Ltd

Shanghai Slamtec Co., Ltd.

Shanghai Marine Diesel Engine Research Institute

Shanghai Centre of Research & Development of New Drugs

Shanghai Newsummit Biopharma Co., Ltd

Shanghai Yizhong Biotechnology Co., Ltd

Yi Lu

Yihui Lin

Guangping Gao

Phillip D Zamore

Tao Wang

Xiang Hu

Jia Pan

Phillip Tai

Qin Zhang

Junjun Xing

Xiaona Zhu

Ying Jiang

Xukun Zhang

Qiang Zheng

Changyong Xiao

Hua Wang

Liang Wang

Jiang Li

Wenjie Zhu

Xiaobo Li

Jing Bai

Le Li

Yuxiang Li

Xun Xu

Xin Gao

Longjie Zhao

Jiye Yang

Sheng Bi

Teng Shen

Yiran Liu

Zhenhua Wang

Shi Bo Zhang

Xiaohui Zhuang

Jiuru Sun

Jian Fei

Xuan Huang

Chong Chen

Lili Shi

Dafu Cui

Li Cao

Youshang Zhang

Yangbin Huang

Kaige Gao

Jialin Zhao

Mingshan Guo

Zhipeng Hou

Chunlei Hong

Xizhao Zhang

Wenjie Kong

Xu Xun

Yuanyuan Huang

A method for forming a semiconductor structure in provided. The method includes providing a substrate, forming a gate electrode layer on the substrate, and performing a defluorination treatment on the gate electrode layer. The method also includes, after performing the defluorination treatment, forming a barrier layer on a portion of a surface of the gate electrode layer. The barrier layer is made of a material including titanium element.

Method for forming semiconductor structure

The disclosure relates, in some aspects, to compositions and methods for treating corneal disease (e.g., corneal neovascularization. In some embodiments, the disclosure relates to rAAV-mediated delivery of an cornea-associated transgene to a subject. In some embodiments, the rAAV transduces the corneal tissue of a subject.

Anti-angiogenic miRNA therapeutics for inhibiting corneal neovascularization

A reaction device of a marine SCR system comprises a conveying unit (), a reaction chamber (), at least one catalyst module (), and an air homogenization chamber (), wherein, the conveying unit () includes an input pipeline () and an output pipeline () sleeved outside the input pipeline (). One end of the reaction chamber () is connected to the conveying unit (). The reaction chamber () comprises an inner cylinder () and an outer cylinder () sleeved outside the inner cylinder (), the inner cylinder () is in communication with the input pipeline (), and the outer cylinder () is in communication with the output pipeline (). The catalyst module () is provided between the inner cylinder () and the outer cylinder (). The air homogenization chamber () is connected to the other end of the reaction chamber () and is in communication with both the inner cylinder () and the outer cylinder (). With the reaction device of the marine SCR system whereby the outer cylinder is sleeved outside the inner cylinder, flue gas from the inner cylinder is turned by the air homogenization chamber and then flows back into the outer cylinder. This can not only substantially reduce the size of the reaction device to improve the integration of the SCR system, but also allow the flue gas to turn in the air homogenization chamber and then flow back, so that the flue gas and a reducing agent can be fully mixed in the air homogenization chamber to improve the catalytic reaction efficiency.

Reaction device of marine SCR system

Semiconductor structure and its fabrication method are provided. The method includes providing a substrate, where the substrate includes a first region having a first metal structure and a second region having a second metal structure; forming a device layer on each of top surfaces of the substrate, the first metal structure and the second metal structure; forming a first through hole in the device layer at the first region, where the first through hole exposes at least a portion of surfaces of the first metal structure, and forming a second through hole in the device layer at the second region, where the second through hole passes through the first device and exposes at least a portion of surfaces of the second metal structure; and using a selective metal growth process, forming a first plug in the first through hole and forming a second plug in the second through hole.

Forming metal plug through a hole in a device including a resistance layer and contacting embedded conductive structures

A task optimization method and a task optimization device in a mobile robot are provided. The task optimization method includes: obtaining at least one task type in a mobile robot and usage information when all users use a task corresponding to each task type; separately performing machine learning on the usage information of all the users corresponding to each task type to obtain at least one piece of user's usage habit information corresponding to each task type and usage probability thereof, thereby performing machine learning on usage information when all users use the task corresponding to the task type; based on the at least one piece of usage habit information corresponding to each task type, the usage probability thereof and the real-time usage information, optimizing the task corresponding to the task type used by the user in real time.

Task optimization method and task optimization device in mobile robot

An image processing method and apparatus, and a storage medium are provided. The method includes: obtaining a first image and a second image of a to-be-authenticated object, where the first image is captured by a first camera module, and the second image is captured by at least one second camera module; comparing the first image with image data in a target library for identity authentication, to obtain a first authentication result; and in response to that the first authentication result is authentication failure, performing joint authentication on the first image and the second image, and determining the identity of the to-be-authenticated object according to a second authentication result of the joint authentication.

Method and apparatus for object authentication using images, electronic device, and storage medium

An IGBT device comprises a super-junction structure arranged in a drift region and formed by a plurality of N-type pillars and a plurality of P-type pillars which are alternately arrayed. Device cell structures of the IGBT device are formed in an N-type epitaxial layer at the tops of super-junction cells. Each device cell structure comprises a body region, a gate structure and an emitter region. N-type isolation layers having a doping concentration greater than that of the N-type epitaxial layer are formed between the bottom surfaces of the body regions and the top surfaces of the P-type pillars and are used for isolating the body regions from the P-type pillars. The super-junction structure and the N-type isolation layers can increase the current density of the device, decrease the on-state voltage drop of the device and reduce the turn-off loss of the device.

IGBT device

A super-junction IGBT device comprises a plurality of N-type pillars and a plurality of P-type pillars which are alternately arrayed in a horizontal direction. Device cell structures are formed at tops of super-junction cells and each comprise a trench gate having a gate trench striding across an interface of the corresponding P-type pillar and the corresponding N-type pillar. A body region is formed at a top of the corresponding N-type pillar, and a source region is formed on a surface of the body region. The top of each N-type pillar is provided with one body region and two trench gates located on two sides of the body region, and each body region is isolated from the P-type pillars on the two sides of the body region through the corresponding trench gates. The invention further discloses a method for manufacturing a super-junction IGBT device. Self-isolation of the P-type pillars is realized, the on-state current capacity of the device is improved, and the on-state voltage drop of the device is reduced.

Super-junction IGBT device and method for manufacturing same

A method for managing storage performance consistency, where the method determines a target throughput for writes to a memory sub-system, increases a tracking variable with a granularity based on the target throughput at fixed intervals, decreases the tracking variable based on writes of host data received from a host system to the memory sub-system, and adjusts a priority of host data writes to the memory sub-system relative to writes of reclaimed data from the memory sub-system in response to the tracking variable indicating a deviation from the target throughput.

Managing storage performance consistency with feedback control

A method for fabricating a semiconductor device includes forming a plurality of gate structures, a source/drain doped layer, a barrier layer, and a dielectric layer on a base substrate. The barrier layer covers the entire top surfaces of the plurality of gate structures. The dielectric layer covers the source/drain doped layer, the barrier layer, and the gate structures. The method further includes forming a plurality of first vias in the dielectric layer on both sides of each gate structure above the source/drain doped layer; forming a plurality of second vias on the gate structures to expose the barrier layer; performing a pre-amorphizing implantation process on the surface of the source/drain doped layer at the bottom of the first vias; removing the barrier layer at the bottom of the second vias; and forming a metal silicide layer on the surface of the source/drain doped layer through a metal silicidation process.

Semiconductor devices and fabrication methods thereof

The present invention provides a novel fusion protein suitable for high expression and the production method thereof. The structure of the fusion protein is A-C1-K-(B-C2-K)n-D, wherein A is the upstream peptide; each of C1 and C2 is independently short peptides having 20-40 amino acids in length and containing no Lys in sequence; K is Lys; B is a linker; D is a downstream peptide; n is an integer of 3-30. The fusion protein is expressed with high efficiency and stability in host cells. The purification and enzymatic cleavage technology of the expression product is simple, which is able to produce a short peptide with high efficiency, and has very high value of industrialization.

Fusion protein suitable for high efficiency expression and the production method thereof

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Shanghai, China

Yi Lu