Qisda Corporation

Yi-Lon Chin

Chang-Hung Lee

The timing synchronization module includes a phase locked loop (PLL) and a synchronization processing unit. The PLL receives an output-end clock signal. When the PLL receives the output-end clock signal for the first time, the PLL generates a reception-end clock signal according to the output-end clock signal. The synchronization processing unit receives a procedure clock signal and the reception-end clock signal. The output-end clock signal has M clocks after the reception-end clock signal is generated, while the reception-end clock signal has N clocks as generated. When the difference value of M and N is larger than a preset value, the synchronization processing unit removes the media signal corresponding to the procedure clock signal and generates the reception-end clock signal again. When the difference value is smaller than the preset value, the synchronization processing unit controls media signal playing according to the reception-end clock signal and the procedure clock signal.

Timing synchronization module and method for synchronously playing a media signal

A method for transferring data by an AV playback system. The AV playback system includes a transmitting terminal and a receiving terminal connected to the transmitting terminal via a network. The receiving terminal includes a receiving buffer, a decoder buffer, and a play-out buffer. The method includes transmitting a first format data from the transmitting terminal to the receiving terminal via the network; stopping transmitting the first format data from the transmitting terminal to the receiving terminal; cleaning data in the receiving buffer, data in the decoder buffer, and data in the play-out buffer; and transmitting another format data different from the first format data from the transmitting terminal to the receiving terminal via the network.

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Yonghe, Taiwan

Yi-Lon Chin