Advanced Micro Devices Corporation

Ess Technology, Inc.

Yi Liu

Geoffrey S Strongin

Michael R Tucker

Frank J Gorishek

Wei-Lien Hsu

Chung-Ta Lee

David C Horton

Lei Cheng

Wei-Lien Hus

Michael Y T Hwang

A memory control apparatus for block-matching motion estimation and an associated search pattern for processing video sequence in real-time are described in this disclosure. The motion estimation subsystem utilizes a set of memory banks to store a section of the reference picture used for computing the differences between an underlying block and a spatially shifted reference block. The memory control apparatus derives the memory addresses for storing the reference picture region in the memory banks in such a way that a row or a column of data from the reference block can be accessed in parallel without wait. The row- or column-data are then made available to the parallel computation unit for computing the block difference in a single processing cycle. An associated spiral search pattern that covers the whole search region is also described that minimizes the required data access and consequently saves power consumption. Combined with a search-stop criterion, the search pattern will result in early search termination during the block-matching motion estimation process and consequently conserves more power.

Memory control apparatus and efficient search pattern for block-matching motion estimation

A method is disclosed for performing an inverse discrete cosine transform (IDCT) using a microprocessor having an instruction set that includes SIMD floating-point instructions. In one embodiment, the method includes: (1) receiving a block of integer data having C columns and R rows; and (2) for each row, (a) loading the row data into registers; (b) converting the row data into floating-point form so that the registers each hold two floating-point row data values; and (c) using SIMD floating-point instructions to perform weighted-rotation operations on the values in the registers. Suitable SIMD floating-point instructions include the pswap, pfmul, and pfpnacc instructions. For the row-IDCT, the data values are preferably ordered in the registers so as to permit the use of these instructions. For the column-IDCT, two columns are preferably processed concurrently using SIMD instructions to improve computational efficiency. An intermediate buffer may be used to avoid unnecessary conversions between integer and floating-point format.

Two-dimensional inverse discrete cosine transform using SIMD instructions

A system and method for carrying out a two-dimensional forward and/or inverse discrete cosine transform is disclosed herein. In one embodiment, the method includes, but is not necessarily limited to: (1) receiving multiple data blocks; (2) grouping together one respective element from each of the multiple data blocks to provide full data vectors for single-instruction-multiple-data (SIMD) floating point instructions; and (3) operating on the full data vectors with SIMD instructions to carry out the two dimensional transform on the multiple data blocks. Preferably the two dimensional transform is carried out by performing a linear transform on each row of the grouped elements, and then performing a linear transform on each column of the grouped elements. The method may further include isolating and arranging the two dimensional transform coefficients to form transform coefficient blocks that correspond to the originally received multiple data blocks. The multiple data blocks may consist of exactly two data blocks. The method may be implemented in the form of software and conveyed on a digital information storage medium or information transmission medium. The dual forward or inverse discrete cosine transform methodology may be employed within a general purpose computer or within a computation unit of a multimedia encoder or decoder system, implemented either in hardware or software. A multimedia encoder or decoder employing the fast, forward or inverse discrete cosine transform methodology in accordance with the present invention may advantageously achieve high performance

Dual-block inverse discrete cosine transform method

The invention, in a first aspect, is a method for mitigating edge effects in a decompressed video image. The method comprises first reads an N&times;N group of pixels defining a vertical edge between two blocks in a video frame row by row into N registers, wherein N is a predetermined number defining the length of a filter. The content of the N registers is then transposed and then filtered in the filter. The filtered content of the N registers is then transposed and stored back from where it was read. In other aspects, the invention is a program storage device encoded with instructions that, when executed by a computer, perform such a method; a computer programmed to perform such a method; and a computing system capable of performing such a method.

Parallel edge filters in video codec

A method for performing fast multiplication in a microprocessor is disclosed. The method comprises detecting multiplication operations that have a floating point operand and an integer operand, wherein the integer operand is an integer power of two. Once detected, a multiplication operation meeting these criteria may be executed by using an integer adder to sum the integer power and the floating point operand's exponent to from a product exponent. The bias of the integer operand's exponent may also be subtracted. A product mantissa is simply copied from the floating point operand's mantissa. The floating point operand's sign bit may be inverted to form the product's sign bit if the integer operand is negative. Advantageously, the product is generated using integer addition which is faster than floating point multiplication. The method may be implemented in hardware or software.

Fast multiplication of floating point values and integer powers of two

A video decoder system affords playback of video information corresponding to a compressed video bitstream which demands less processor performance than would be demanded for decoding the compressed video bitstream itself. One embodiment includes preprocessing and partially decoding the compressed video bitstream, and retaining the partially-decoded information for subsequent playback. In another embodiment the compressed video bitstream is preprocessed and information useful for increasing the processing speed is retained for subsequent playback. Either embodiment may be used alone, or both may be used together. The information useful for increasing the processing speed which is retained for subsequent playback may be retained by creating an intermediate video bitstream which may include partially decoded information from the compressed video bitstream as well as the information useful for increasing the processing speed of the video information. The intermediate video bitstream may be stored on a system hard disk where it may be read much faster than if stored on a CD-ROM and may be deleted when not needed.

Generation of an intermediate video bitstream from a compressed video

A method and apparatus for decoding variable length code (VLC) data employ a hybrid technique of parsing short-length VLC codes using a binary tree or binary search procedure and parsing longer VLC codes using a table lookup procedure. This technique includes the steps of accessing a plurality of bits of coded bitstream data, bit testing a preselected number N first bits of the plurality of bitstream bits and determining whether the N first bits include a complete VLC code. If the N first bits include a complete VLC code, a VLC code is decoded in accordance with a result of the bit testing step. If the N first bits do not include a complete VLC code, a VLC code is decoded from a lookup table to a table element addressed by the bits of coded bitstream data.

Method and apparatus for hybrid VLC bitstream decoding

A video decoding system examines a block of DCT coefficients prior to computation of an inverse discrete cosine transform (IDCT) to determine the number of nonzero coefficients. A plurality of IDCT engines are available in the video system including an IDCT engine utilizing fewer computations for a sparse picture and an IDCT engine utilizing fewer computations for a nonsparse picture. The video decoding system selects an IDCT engine to minimize the number of computations performed and to thereby reduce the computational burden of IDCT transformation.

Method and apparatus for improved video decompression by selection of

A video decoding system that selectively arranges video information within a memory to correspond to macroblocks of video information. Such a system advantageously increases the efficiency of processing video information when decoding compressed video information.

Performance of video decompression by using block oriented data

A video decoding apparatus and method greatly reduces the computational burden of video decoding by processing several pixels in parallel, thereby reducing the computational load by a factor approximating the number of pixels processed at one time.

Method and apparatus for improved video decompression by prescaling of

A method of adaptively performing motion compensation in a video processing apparatus is provided. The video processing apparatus processes macroblocks of compressed video information. Some of these macroblocks have motion vectors associated therewith. The method is conveniently implemented on a general purpose computer in one embodiment. In accordance with the disclosed method, the performance of the processor in the computer is monitored and a measurement of this performance is made. A threshold dependent on the measured processor performance is then set. For those macroblocks which have motion vectors associated therewith, the magnitude of the motion vector is determined. If the magnitude of the motion vector of a particular macroblock exceeds the threshold, then motion compensation is performed on that macroblock. However, if the magnitude of the motion vectors or motion vectors associated with a particular macroblock do not exceed the threshold, then no motion compensation is performed. The processor is thus relieved from the computational burden of performing motion compensation on a significant number of macroblocks.

Method and apparatus for adaptively performing motion compensation in a

A decoding system stores frequently-occurring DCT coefficient blocks in a memory and stores pre-computed spatial domain kernels which correspond to the stored DCT coefficient blocks. The video system examines a block of DCT coefficients prior to computation of an inverse discrete cosine transform (IDCT) to determine whether the block is substantially similar to a stored frequently-occurring DCT coefficient block. If so, the spatial domain kernel corresponding to the frequently-occurring DCT block is utilized in the decoded picture, bypassing computation of the IDCT.

Method and apparatus for improved video decompression by

A video system examines the transform domain content of various spatially related blocks in a compressed video bitstream to determine whether predetermined types of similarities exist between multiple blocks. When certain selected similarities are found, the video system spatially combines the blocks in a predetermined manner. In some embodiments, DCT coefficients of a plurality of blocks are averaged to form one averaged block and the averaged block is inverse discrete cosine transformed. The averaged and IDCT transformed block is written to the display at the position of each of the averaged blocks. In some embodiments, a representative block of a plurality of DCT coefficient blocks is selected and inverse discrete cosine transformed. The selected and IDCT transformed block is written to the display at the position of each of the plurality of blocks.

Method and apparatus for improved video decompression by selective

An video decoder system, such as for use with MPEG video compression, uses a previous B-frame as an additional prediction source for the current B-frame. In one embodiment, a given block within a current B-frame 'N' reuses IDCT result terms from the previous B-frame 'N-1' if they are determined to be 'similar enough' to the anticipated IDCT result terms which would otherwise need to be computed. For a given block, each of the 'M' lowest-frequency DCT coefficients for B-frame 'N' and B-frame 'N-1' are respectively compared: if they differ by less than a similarity threshold value, then the IDCT result terms from the previous B-frame 'N-1' are reused without further computation. The similarity threshold may be adaptively adjusted to reduce the computational burden of video decompression, while affording a gradual degradation of picture quality, rather than wholesale skipping of entire frames.

Method and apparatus for improved video decompression using previous

A DCT VLC decoding method substantially lessens the computational burden of picture dequantization. The method of decoding variable length code (VLC) data includes the step of receiving a bitstream sequence organized into a hierarchy of levels including, in order, a sequence layer, a group of pictures layer, a picture layer, a slice layer, a macroblock layer, and a block layer. In the sequence layer, the method defines a quantization matrix. In a macroblock layer, the method defines a quantizer scale parameter in the macroblock layer, multiplies the quantization matrix times the quantizer scale parameter and stores the product in a quantization multiplication factor. In the block layer, the method parses an encoded data bitstream to detect a VLC code in the block layer and dequantizes the VLC code by multiplying the VLC code times the quantization multiplication factor.

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Austin, TX, United States of America

Yi Liu