Taiwan Semiconductor Manufacturing Comp. Ltd.

Himax Imaging, Inc.

United Microelectronics Corp.

Yi-Lin Tsai

Jing-Cheng Lin

Jui-Pin Hung

Chih-Hao Chen

Chung Yu Wang

Kung-Chen Yeh

Long Hua Lee

Chun-Hsing Su

Hsien-Wen Liu

Nai-Wei Liu

Tsei-Chung Fu

Jeffrey Chang

Chin-Fu Kao

Chin-Chuan Chang

Yi-Chao Mao

Yuan-Chih Peng

Chih-Hsien Tang

Shih-Yi Syu

Ying-Tz Hung

Su-Yun Fang

An imprint method includes the following steps. A first resist layer is formed on a first substrate. A first imprinting step using a first mold is performed to the first resist layer. A first etching process is performed to the first substrate with the first resist layer as an etching mask after the first imprinting step so as to form a first recess pattern in the first substrate. A second resist layer is formed on the first substrate. A second imprinting step using a second mold is performed to the second resist layer. A second etching process is performed to the first substrate with the second resist layer as an etching mask after the second imprinting step so as to form second recess patterns in the first substrate. A depth of the first recess pattern is greater than a depth of each of the second recess patterns.

Imprint method

A package includes a device die, a molding material molding at least a portion of the device die therein, and a through-via substantially penetrating through the molding material. The package further includes a dielectric layer contacting the through-via and the molding material, and a die attach film attached to a backside of the device die. The die attach film includes a portion extending in the dielectric layer.

Fan-out POP structure with inconsecutive polymer layer

A method includes molding a polymer onto a package component. The step of molding includes a first molding stage performed at a first temperature, and a second molding stage performed at a second temperature different from the first temperature.

Methods for molding integrated circuits

Fan-out PoP structure with inconsecutive polymer layer

A wafer level package includes a semiconductor die bonded on a supporting wafer. The semiconductor die has at least a step recess at its substrate. An underfill layer is formed between the semiconductor die and the supporting wafer. Moreover, the height of the underfill layer is limited by the step recess. During a fabrication process of the wafer level package, the step recess helps to reduce the stress on the wafer level package.

Package for three dimensional integrated circuit

A bad pixel correction method for an image is provided. The bad pixel correction method includes the steps of determining whether each of pixels of a predetermined block in the image is a bad pixel sequentially; when a current pixel of the block is determined to be bad and a temperature value is higher than a threshold, re-determining that at least one previously determined pixel in the predetermined block to be bad; and correcting the current pixel and the previously determined pixel, wherein the previously determined pixel is adjacent to the current pixel.

Image processing method and image processing device

An image processing module is provided. A de-mosaic unit in the image processing module includes an edge direction detection unit and a multi-pixel directional interpolation unit. The edge direction detection unit is used to determine a first color row luminance difference according to a plurality of first color pixels of a pixel row of raw data, and determine a first color column luminance difference according to a plurality of first color pixels of a pixel column of raw data. The multi-pixels directional interpolation unit is used to determine pixel luminance of a third color array according to the first color column luminance difference, the first color row luminance difference, the third color pixels adjacent to a first color pixel and the third color pixels adjacent to a second color pixel.

A method includes performing a dicing on a composite wafer including a plurality of dies, wherein the composite wafer is bonded on a carrier when the step of dicing is performed. After the step of dicing, the composite wafer is mounted onto a tape. The carrier is then de-bonded from the composite wafer and the first tape.

Methods for de-bonding carriers

Growing community of inventors

Tainan, Taiwan

Yi-Lin Tsai