Global Unichip Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Yi-Lin Lee

Yen-Chung Chen

Wen-Juh Kang

Tsai-Ming Yang

Yu-Chu Chen

Yen-Chung Tony Chen

Ju-Chieh Wang

Jen-Tai Hsu

Ting-Hsu Chien

Fu-Tai An

An amplifier circuitry includes a current source circuit, a voltage regulator circuit, and an amplifier. The current source circuit generates a first bias current. The voltage regulator circuit regulates a reference voltage to generate a supply voltage. The voltage regulator circuit includes a first and a second compensation resistors, the first and the second compensation resistors are configured to generate the reference voltage according to a reference a second bias currents, and a first ratio is present between the first and the second biasing currents. The amplifier includes first load resistors which are configured to generate a first common-mode output signal based on the supply voltage and the first bias current. The second ratio is present between the second compensation resistor and one of the first load resistors, and the first and the second ratios are arranged to compensate the first common-mode output signal.

Amplifier circuitry, voltage regulator circuit, and signal compensation method

A clock and data recovery module includes a clock and data recovery loop and a spread spectrum clock tracking circuit. The clock and data recovery loop includes a clock and data recovery unit and a first phase interpolator. The first phase interpolator is coupled to the clock and data recovery unit and configured to generate a data clock signal and an edge clock signal according to a phase signal and a reference clock signal. The clock and data recovery unit is configured to generate the phase signal according to a data signal, the data clock signal and the edge clock signal. The spread spectrum clock tracking circuit is configured to generate the reference clock signal according to the data signal, and to transmit the reference clock signal to the first phase interpolator. The spread spectrum clock tracking circuit is decoupled to the clock and data recovery loop.

Clock and data recovery module

A receiving device includes a first calculating circuit, an error slicer, a data slicer, a second calculating circuit, and an equalization circuit. The first calculating circuit is configured to generate a calculating signal according to an equalized signal and a feedback signal. The error slicer is configured to generate an error signal according to the calculating signal. The data slicer is configured to generate a data signal according to the calculating signal. The second calculating circuit is configured to generate a first, a second, and a third equalization coefficient according to the data signal and the error signal. The equalization circuit is configured to generate the feedback signal according to the first, the second, and the third equalization coefficient. A gain value of the equalization circuit is associated with the first equalization coefficient. A time constant of the equalization circuit is associated with the second and the third equalization coefficient.

Receiving device and signal conversion method

A latch circuit including a symmetric circuit, a clock receiving circuit, a current generating circuit, a sampling circuit and a holding circuit is provided. The clock receiving circuit receives a first clock signal and a second clock signal. A phase difference between the first clock signal and the second clock signal is 180 degrees. The current generating circuit is electrically connected with the symmetric circuit and the clock receiving circuit, for providing a discharge current. The sampling circuit is electrically connected with the current generating circuit. According to the first clock signal, the sampling circuit receives a differential input signal, and the discharge current flows through the sampling circuit. The holding circuit is electrically connected with the current generating circuit. According to the second clock signal, the discharge current flows through the holding circuit, and the holding circuit generates a differential output signal.

Current-mode logic latch circuit

A phase interpolator including a phase interpolation circuit, a plurality of low pass filtering channels, and a multiplexing circuit is provided. The phase interpolation circuit receives a first clock signal and a second clock signal and accordingly performs an interpolation operation to generate an output clock signal. The low pass filtering channels respectively have an output terminal and an input terminal that is coupled to the phase interpolation circuit to receive the output clock signal. Each of the low pass filtering channels includes a switch and a capacitor which are coupled to a common node as the output terminal. The multiplexing circuit has a plurality of input terminals respectively coupled to the output terminals of the low pass filtering channels. The multiplexing circuit selects an input signal received from one of the low pass filtering channels as a phase interpolation signal according to a selecting signal.

Phase interpolator and clock and data recovery circuit

A receiver is provided. The receiver includes a CTLE receiving a received signal, and generating a first equalized signal by processing the received signal according to a pole and a boost level; a slicing circuit coupled to the CTLE, generating a data signal according to the first equalized signal and a feedback equalization signal; a DFE coupled to the slicing circuit, generating the feedback equalization signal by processing the data signal according to a DFE coefficient set. Furthermore, the boost level is adjusted according to a first DFE coefficient of the DFE coefficient set, while the pole is adjusted according to the second and third DFE coefficients.

Receiver and associated control method

An active inductor includes a first transistor, a capacitor, a second transistor, a first resistor, a second resistor, and a bias current source. A source terminal of the first transistor is a first terminal of the active inductor and connected to a first voltage source. The capacitor is connected to the source terminal and gate terminal of the first transistor. A drain terminal of the second transistor is connected to the source terminal of the first transistor. A gate terminal of the second transistor is connected to a drain terminal of the first transistor. The first resistor is connected between the drain terminal of the first transistor and a second terminal of the active inductor. The second resistor is connected to a source terminal of the second transistor. The bias current source is connected between the second resistor and a second voltage source.

Active inductor and associated amplifying circuit

A current-mode D latch includes a first load element, a second load element, a first bias current source, a first switch transistor, a second switch transistor, a first stage circuit and a second stage circuit. The first switch transistor is controlled by an inverted reset signal. The second switch transistor is controlled by a reset signal. When an inverted clock signal is in a first level state and the reset signal is inactive, the first input signal is converted into the first output signal and the first inverted input signal is converted into the first inverted output signal by the first stage circuit. When a clock signal is in the first level state and the reset signal is inactive, the first output signal and the first inverted output signal are maintained by the second stage circuit.

Current-mode D latch with reset function and associated circuit

This invention provides a clock and data recovery system, which comprises a plurality of gm cells, control device, resistor and capacitor. The gm cells respectively have an input end and an output end. The control devices are connected to these output ends. According to a time value, the control device controls a part of the plurality of gm cells to form a first gm cell, and the control device controls another part of the plurality of gm cells to form a second gm cell. The resistor is connected between the first gm cell and the second gm cell. The capacitor is connected to the second gm cell. Wherein, the control device controls the ratio of the first gm cell and the second gm cell in accordance with a time-division multiplexed manner.

Growing community of inventors

Hsinchu, Taiwan

Yi-Lin Lee