Via Technologies, Inc.

Other

Tian Holdings, LLC

Kinpo Electronics, Inc.

Via Optical Solution, Inc.

Moai Electronics Corporation

Yi-Lin Lai

Chin-Yin Tsai

Sung-Hung Li

Chen-Te Chen

Sue-Hong Chou

Yi-Sung Chan

Wei-Ming Su

Hao-Hsuan Chiu

Terrance Shih

Kuo-Yu Wu

Yao-Shun Hung

Bo-Ming Huang

Ying-Che Chung

Sheng-Huei Huang

Jiin Lai

Shih-Fang Chen

Yi-Chung Chan

Hung-Chang Chen

Terrance Shiyang Shih

Keng-Lon Lei

Ching-Yu Chen

Ting-Wen Su

Pei-Jei Hu

Tien-Yu Pan

Chia-Ying Kuo

Shin Yung Chen Banyan

Woei-Harng Lin

Banyan Shin Yung Chen

Shih-Lung Ouyang

Jay Hu

Fu-Sheng Huang

Sl Ouyang

I-Ming Sing

Tuo-Jen Chen

Saga Wang

A data storage system and a global deduplication method thereof are provided. The data storage system includes multiple storage devices and one dispatch device. The dispatch device divides an original data corresponding to a data writing request into at least one data chunk. The dispatch device performs a summary calculation on one data chunk, so as to generate a representative value. The dispatch device performs a first distribution calculation on the representative value, so as to determine a destination location corresponding to the representative value. The dispatch device transmits the data chunk and the representative value to at least one destination storage device among the storage devices through a communication network according to the destination location. The at least one destination storage device checks the representative value, so as to determine whether to store the data chunk in a storage space of the at least one destination storage device.

Data storage system and global deduplication method thereof

A computing apparatus includes a first processing circuit and a second processing circuit. The first processing circuit includes a programmable logic circuit. The second processing circuit includes a general purpose processor that is used to execute an application program to download a bitstream to the first processing circuit for programming the programmable logic circuit to implement a direct memory access (DMA) engine and at least one physical engine (PE). The DMA engine is used to access a first memory through a DMA manner. The at least one PE is used to read data to be processed from the first memory through the DMA engine. The first processing circuit and the second processing circuit are disposed in one chip.

Computing apparatus utilizing programmable logic circuit to implement direct memory access engine and at least one physical engine and providing data to be processed to at least one physical engine through direct memory access engine

A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a first cyclic redundancy check (CRC) circuit, a second CRC circuit, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The interface circuit receives and provides a first data portion of the decoded codeword to a host. The first CRC circuit performs a first CRC on the first data portion and generates a check status message based on a relationship between a result of the first CRC and a first CRC code of the decoded codeword. The second CRC circuit performs a second CRC on the first data portion to generate a second CRC code. The second CRC circuit determines whether to further change the second CRC code to make the second CRC code not match the first data portion according to the check status message.

Non-volatile memory apparatus and reading method thereof

A non-volatile memory apparatus includes an error checking and correcting (ECC) decoding circuit, a main buffer circuit, a multiplexer, and an interface circuit. The ECC decoding circuit decodes an original codeword to obtain a decoded codeword. The main buffer circuit is coupled to the ECC decoding circuit for receiving and storing a first data portion of the decoded codeword. The multiplexer's first input end is coupled to the output end of the main buffer circuit. The second input end of the multiplexer is coupled to the output end of the ECC decoding circuit. The interface circuit is coupled to the output end of the multiplexer and receives the first data portion from the multiplexer to provide the first data portion to a host.

An error checking and correcting (ECC) decoding method and apparatus are provided. A decoding circuit decodes a codeword using (or without using) reference information, wherein when the decoding circuit fails to decode a first codeword, the decoding circuit decodes a second codeword to produce decoded data. The decoding circuit checks whether a change has occurred from each codeword bit of the second codeword to a corresponding bit of the decoded data. In accordance with a bit position of the changed corresponding bit, the decoding circuit correspondingly changes the first codeword to a modified codeword, and/or correspondingly changes the reference information to modified information. The decoding circuit performs the ECC decoding again on the modified codeword (or the first codeword) using (or without using) the modified information.

Error checking and correcting decoding method and apparatus

An interface controller coupling the main body of an external electronic device to a host, and the electronic device using the interface controller and a control method for the external electronic controller are disclosed. The interface controller has a control unit and a non-volatile memory. The control unit is configured to transmit a termination-on signal to the host when link information retrieved from the main body has been written into the non-volatile memory. When the host issues a link information request in response to the termination-on signal, the control unit uses the link information stored in the non-volatile memory to respond to the link information request.

Interface controller, external electronic device, and external electronic device control method

A non-volatile memory apparatus including a non-volatile storage circuit, a main memory and a controller, and an operating method thereof are provided. Each of a plurality of logical block address groups includes a plurality of logical block addresses. Each of the logical block address groups is assigned with a group age parameter. The adjusting of the group age parameters is triggered by a writing instruction of a host. When an age parameter of the group age parameters exceeds a predetermined range, the controller performs a scanning operation to the non-volatile storage blocks of the non-volatile storage circuit corresponding to a corresponding logical block address group of the age parameter, so as to check an error-bit quantity. The controller decides whether the storage block data-moving operation is performed to the non-volatile storage block corresponding to the corresponding logical block address group based on the results of the scanning operation.

Non-volatile memory apparatus and operating method thereof

A memory apparatus and an energy-saving control method thereof are provided. The internal clock signal sent to a specific circuit group is stopped outputting when it is determined that no processing command is to be processed currently and current events are finished being processed, so as to reduce power consumption of a control chip.

Memory apparatus and energy-saving control method thereof

A memory apparatus and an energy-saving control method thereof are provided. The memory apparatus includes a plurality of non-volatile memory units and a control chip, and the control chip includes a specific circuit group, a memory control unit and an energy-saving control unit. The memory control unit controls an access to the non-volatile memory units. In a normal mode and during a period of accessing the non-volatile memory units by the control chip, if the non-volatile memory units are in a busy state, the energy-saving control unit controls the clock generation unit to stop outputting an internal clock signal to the specific circuit group, so as to reduce power consumption of the control chip.

A memory chip coupled to a host includes a memory and a controller. The memory is pre-loaded with a plurality of boot images, wherein the boot images have the same content. The controller is coupled to the memory, and processes data transmissions between the memory chip and the host, wherein the controller further determines whether the memory chip enters a boot mode for the first time, and when the memory chip enters the boot mode for the first time, the controller accesses the memory to obtain a correct boot image from the boot images and transmits the correct boot image to the host. Further, each boot image includes a plurality of data blocks, and the controller loads a plurality of correct data blocks from one or more of the boot images to obtain the correct boot image.

Memory chips and data protection methods

A non-volatile memory apparatus including a non-volatile storage circuit, a main memory and a controller, and an operating method thereof are provided. Each of a plurality of logical block address groups includes a plurality of logical block addresses. Each of the logical block address groups is assigned a group read-count value. An adjustment of the group read-count values is triggered by a read command of a host. When one read-count value of the group read-count values exceeds a preset range, the controller performs a scan operation to non-volatile storage blocks of the non-volatile storage circuit corresponding to a corresponding logical block address group of the read-count value, so as to check a number of error bits. The controller decides whether to perform a storage block data-moving operation to the non-volatile storage block corresponding to the corresponding logical block address group based on results of the scan operation.

A flash memory control technique with high reliability is provided. A flash memory controller provides a volatile storage area for temporary storage of logical-to-physical address mapping data between a host and a flash memory as well as error detection codes encoded from the logical-to-physical address mapping data. When reading from the volatile storage area, the microcontroller of the flash memory controller is configured to perform an error detection procedure based on the error detection codes. The microcontroller is further configured to restore the logical-to-physical address mapping data in the volatile storage area based on a backup of the logical-to-physical address mapping data.

Flash memory controller, data storage device, and flash memory control method with volatile storage restoration

A memory chip coupled to a host includes a memory and a controller. Multiple boot images having the same content are pre-loaded in the memory. The controller is coupled to the memory for processing data transmission between the memory chip and the host. The controller further determines whether the memory chip enters a boot mode for the first time. When the memory chip enters the boot mode for the first time, the controller accesses the memory so as to obtain a correct boot image from the boot images and transmits the correct boot image to the host.

A flash memory control method, storing a logical-to-physical address mapping relationship between a host and a flash memory and a root table in the flash memory and providing a non-volatile storage area storing a root table pointer. A mapping relationship pointer is set forth in the root table to show where the logical-to-physical address mapping relationship is stored in the flash memory. The root table pointer points to the root table stored in the flash memory. In response to a power restoration request issued from the host, the flash memory is accessed based on the root table pointer and thereby the root table is read and the logical-to-physical address mapping relationship is retrieved from the flash memory based on the mapping relationship pointer set forth in the root table.

Flash memory control chip and data storage device and flash memory control method

An overclocking process for a data storage device using a flash memory. A controller for the flash memory tests the flash memory using test clocks with various frequencies to determine at least one clock signal suitable to the flash memory. The clock candidates suitable to the flash memory are selected from the test clocks. The flash memory is operated in a variable-frequency manner by which the flash memory is switched between the clock candidates, such that electromagnetic interference is spread over different bands.

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Taipei, Taiwan

Yi-Lin Lai