Realtek Semiconductor Inc.

Taiwan Semiconductor Manufacturing Comp. Ltd.

Yi-Lin Chen

Chin-Chuan Hsieh

Cheng-Hsin Chang

Szu-Ping Chen

Tsung-Lian Chou

Chih-Hao Chen

The present invention relates to a metal-oxide-semiconductor field-effect transistor (MOSFET) with electrostatic-discharge (ESD) protection and a voltage-stabilizing capacitor, and a method for manufacturing the same and is applied to a chip, including a P-type substrate, a conductor layer, a first N-type doping region, a second N-type doping region, and an N-type well. The conductor layer is coupled to the ground; the first N-type doping region is coupled to the power supply; the second N-type doping region is coupled to a VDD pad (power-supply pad). Thereby, when the chip is not installed or not operating, the MOSFET can be used for ESD protection. When the chip is operating, the conductor layer, the first N-type doping region, the second N-type doing region, and the N-type well form a gate capacitor as a voltage-stabilizing capacitor between the power supply and the ground. Hence, the objective of fully utilization is achieved. In addition, the chip size is saved and thus the cost thereof is reduced.

Metal-oxide-semiconductor field-effect transistor with electrostatic-discharge protection and voltage-stabilizing capacitor and method for manufacturing the same

A digital circuit system includes: a register, for receiving and registering digital data; an operation unit, for operating and generating resulting data according to the digital data registered in the first registering unit; a second register, for receiving and registering the resulting data; a multi-phase clock signal generating unit, for generating a plurality of reference clock signals having different phases with each other; a first selector, for selecting one of the reference clock signals to output a first clock signal to the first registering unit; and a second selector, for selecting another of the reference clock signals to output a second clock signal to the second registering unit.

Clock generating circuit and digital circuit system incorporating the same

A TDC circuit includes: a first delay circuit, including at least one first delay stage for delaying a first input signal to generate a first output signal; a second delay circuit, including at least one second delay stage for delaying a second input signal to generate a second output signal; a first counter, for computing the first output signal to generate a first counter value; a second counter, for computing the second output signal to generate a second counter value; and a comparator, for comparing the first counter value and the second counter value to generate a comparing result signal; wherein the first delay stage has a larger delay amount than the second delay stage, the first counter starts before the second counter, and the comparator outputs the comparing result signal when the second counter value falls within a predetermined range of the first counter value.

Time to digital converting circuit and related method

A method for forming a decouple capacitor of an integrated circuit, the integrated circuit including a core circuit and a plurality of I/O circuits coupled to the core circuit, includes cutting part of a plurality of lines in at least one specific circuit of the I/O circuits to form decouple capacitors of the integrated circuit.

Decouple capacitor forming circuit, integrated circuit utilizing the decouple capacitor forming circuit and related method

A memory controller for controlling a memory, where the memory controller includes: a pad, coupled to the memory, for generating an output signal to the memory according to a signal value of the memory controller; a voltage pull-up device, coupled to the pad, comprising a first N type transistor and for pulling up a voltage level on the pad according to the signal value; and a voltage pull-down device, coupled to the pad, comprising a second N type transistor and for pulling down the voltage level on the pad according to the signal value.

Memory controller and output signal driving circuit thereof

Disclosed is an output driver, which comprises: a resistance element with resistance, coupled to an output terminal; a current mode driving circuit, coupled to the resistance element, for providing a first current to the output terminal, wherein at least one of the amount of the first current and the resistance of the resistance element is adjusted according to a control signal; and a control circuit for generating the control signal according to a mode signal, wherein the mode signal corresponds to at least two technology standards.

Output driving circuit

The present invention relates to a signal transferring system. The signal transferring system includes a first and second layout paths, and a first and second circuits. Lengths of the first and second layout paths are different. The first and second circuits are used for transmitting and receiving at least two signals respectively. In addition, one of the first circuit and the second circuit includes a compensation circuit for adjusting transmission time of one of the at least two transferred signals or adjusting reception time of one of the at least two transferred signals such that the at least two transferred signals reach a second circuit through the first and the second layout paths at substantially the same time.

Signal transferring system with unequal lengths of connecting paths and method thereof

A new method is provided for the creation of an alignment mark. V-groove etching is applied whereby this anisotropic etch stops at the (1,1,1) crystal direction of the silicon of the substrate. The invention applies a wet etchant to the surface of monocrystalline silicon of the silicon substrate by using a solution containing a mixture of potassium hydroxide (KOH) or NHor tetramethyl ammonium hydroxide (TMAH). This solution anisotropically etches the silicon substrate, forming grooves in the substrate having sidewalls that are sloped at an angle of about 54 degrees with the horizontal. The slope of the sidewalls is a function of the different etch rates of monocrystalline silicon along the different crystalline orientations. The surface of the substrate represents &#x3c;100&#x3e; planes of the silicon, which etches faster than the sloped sidewalls that represent the &#x3c;111&#x3e; plane. The KOH/NH/TMAH etch stops on the &#x3c;111&#x3e; plane of the silicon substrate.

Using V-groove etching method to reduce alignment mark asymmetric damage in integrated circuit process

A new method is provided for the creation of a dummy pattern. A typical wafer exposure mask contains a Clear Out Window (CLWD) pattern, this CLWD pattern is of no value during the process of shielding the area on the surface of the wafer where the alignment mark must be placed. This CLWD can therefore be used to create a dummy overlay pattern, resulting in a reduction in the wafer scaling error that typically occurs as a result of metal deposition. For the same reasons, a dummy overlay pattern can also be created in the scribe lines of the wafer surface.

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Taipei, Taiwan

Yi-Lin Chen