Chartered Semiconductor Manufacturing Ltd (corporation)

Nanyang Technological University

The Texas A&m University System

Singapore Technologies Dynamics Pte Ltd

Singapore Technologies Dynamics Ptd Ltd.

Yi Liang Xu

Simon Yew-Meng Chooi

Mei Sheng Zhou

Subhash Gupta

John Leonard Sudijono

Sudipto Ranendra Roy

Yakub Aliyu

Paul Kwok Keung Ho

Paul Kwok Ho

Mei-Sheng Zhou

Kwok Keung Paul Ho

Shao-fu Sanford Chu

Kai Shao

Cerdin Lee

Jia Zhen Zheng

Meng Hiot Lim

Charles Lin

Jian Xun Li

Magnus A O Hook

Joseph Zhifeng Xie

Subramanian Balakumar

Licheng Han

Xian Bin Wang

Jianxun Li

Yew Soon Ong

Cuiyang Wang

Jane C M Hui

Subbash Gupta

Yih Shung Lin

Guo Li Mike

A method and system are presented for configuring a search algorithm for solving a combinatorial optimization problem. The search algorithm has a number of procedural components. Each procedural component is configured using a respective data structure. The data structure has a tree structure, including traversal split nodes, each of which represents a choice to be made when configuring the procedural component of the search algorithm. Configuring the procedural component corresponds to traversing the tree structure, and the traversal is performed automatically. At each of the traversal split nodes, the choice of which direction to take through the tree structure is made randomly, using a respective probabilistic function. Thus, a population of candidate algorithms is generated. These are evaluated, and the probabilistic functions modified.

Method and apparatus for automatic configuration of meta-heuristic algorithms in a problem solving environment

The invention pertains to an algorithm development environment for solving a class of combinatorial optimization problems. Many practical real-life applications can be formulated as combinatorial optimization problems. Over the years, there have been algorithms proposed to solve these problems. The effort in customizing algorithms to fulfill a particular domain-specific application is still significant. Furthermore, conventional approaches towards codes generation and modification are tedious and thus inefficient. To address the need for rapid generation of algorithms that are efficient in solving a given class of real-life problems, embodiments provide a hierarchical tree structure for managing a procedure modules library. Based on the preferred management and object-oriented design concept, users configure and generate a genetic algorithm (GA) via an intuitive graphical user interface. The goal-seeking customization of the generated GA can be easily carried out for solving various optimization problems. This way, the efficiency of algorithm development is enhanced significantly.

Method and apparatus for an algorithm development environment for solving a class of real-life combinatorial optimization problems

A semiconductor chip having an exposed metal terminating pad thereover, and a separate substrate having a corresponding exposed metal bump thereover are provided. A conducting polymer plug is formed over the exposed metal terminating pad. A conforming interface layer is formed over the conducting polymer plug. The conducting polymer plug of the semiconductor chip is aligned with the corresponding metal bump. The conforming interface layer over the conducting polymer plug is mated with the corresponding metal bump. The conforming interface layer is thermally decomposed, adhering and permanently attaching the conducting polymer plug with the corresponding metal bump. Methods of forming and patterning a nickel carbonyl layer are also disclosed.

Method of copper/copper surface bonding using a conducting polymer for application in IC chip bonding

Isolated peptide sequences and proteins containing these sequences are provided which are useful in the prevention and treatment of infection caused by Gram-positive bacteria. The peptide sequences have been shown to be highly conserved motifs in the surface proteins of Gram-positive bacteria, and these consensus sequences include amino acid sequences such as LPXTG (SEQ ID NO:13), ALKTGKIDIIISGMTSTPERKK (SEQ ID NO:14), VEGAVVEKPVAEAYLKQN (SEQ ID NO:15), and EYAGVDIDLAKKIAK (SEQ ID NO:16). By virtue of the highly conserved regions, the sequences and the proteins including these sequences can be utilized to generate antibodies which can recognize these highly conserved motifs and the proteins containing them and thus be useful in the treatment or prevention of a wide range of infections caused by Gram-positive bacteria.

Surface proteins from gram-positive bacteria having highly conserved motifs and antibodies that recognize them

Method and product for forming a dual damascene interconnect structure, wherein depositing a copper sulfide interface layer as sidewalls to the opening deters migration or diffusing of copper ions into the dielectric material.

Copper diffusion deterrent interface

A method of bonding a wire to a metal bonding pad, comprising the following steps. A semiconductor die structure having an exposed metal bonding pad within a chamber is provided. The bonding pad has an upper surface. A hydrogen-plasma is produced within the chamber from a plasma source. The metal bonding pad is pre-cleaned and passivated with the hydrogen-plasma to remove any metal oxide formed on the metal bonding pad upper surface. A wire is then bonded to the passivated metal bonding pad.

Method of using hydrogen plasma to pre-clean copper surfaces during Cu/Cu or Cu/metal bonding

A method of bonding a bonding element to a metal bonding pad comprises the following steps. A semiconductor structure having an exposed, recessed metal bonding pad within a layer opening is provided. The layer has an upper surface. A conductive cap having a predetermined thickness is formed over the metal bonding pad. A bonding element is bonded to the conductive cap to form an electrical connection with the metal bonding pad.

Method of application of conductive cap-layer in flip-chip, cob, and micro metal bonding

A method for cleaning a semiconductor structure using vapor phase condensation with a thermally vaporized cleaning agent, a hydrocarbon vaporized by pressure variation, or a combination of the two. In the thermally vaporized cleaning agent process, a semiconductor structure is lowered into a vapor blanket in a thermal gradient cleaning chamber at atmospheric pressure formed by heating a liquid cleaning agent below the vapor blanket and cooling the liquid cleaning agent above the vapor blanket causing it to condense and return to the bottom of the thermal gradient cleaning chamber. The semiconductor structure is then raised above the vapor blanket and the cleaning agent condenses on all of the surfaces of the semiconductor structure removing contaminants and is returned to the bottom of the chamber by gravity. In the pressurized hydrocarbon process, a semiconductor structure is placed into a variable pressure cleaning chamber, having a piston which changes the pressure by reducing or increasing the volume of the chamber. The semiconductor structure first exposed to the hydrocarbon in vapor phase, then the piston is lowered to condense the hydrocarbon. A semiconductor structure can be cleaned by either or both of these processes by repetitive vaporization/condensation cycles.

Method for cleaning semiconductor structures using hydrocarbon and solvents in a repetitive vapor phase/liquid phase sequence

A damascene structure with reduced capacitance dielectric stacking comprise a passivation, a first dielectric, an etch stop, a second dielectric and a cap layer over a first conductive layer formed on a semiconductor. The passivation, the etch stop, and the cap layers comprise low dielectric constant materials carbon nitride, boron nitride, or boron carbon nitride. The stack is patterned to form a via opening to the first conductive layer. A trench opening is formed stopping on the etch stop layer. A barrier layer of TaN, WN, TaSiN or Ta and a second conductive material is applied to the openings. Passivation, etch stop, or cap layers can be formed with carbon nitride by magnetron sputtering from a graphite target in a nitrogen atmosphere; boron carbon nitride by magnetron sputtering from a graphite target in a nitrogen and B H atmosphere; or boron nitride by PECVD using B H , ammonia, and nitrogen.

Damascene structure with reduced capacitance using a boron carbon nitride passivation layer, etch stop layer, and/or cap layer

Method to create a copper diffusion deterrent interface

A new method to prevent oxide erosion in a metal plug process by employing a silicon nitride layer over the oxide is described. An oxide layer is deposited overlying a semiconductor substrate. A silicon nitride layer is deposited overlying the oxide layer. An opening is etched through the silicon nitride layer and into the oxide layer. A barrier metal layer is deposited overlying the silicon nitride layer and into the opening. A metal layer is deposited overlying the barrier metal layer. The metal layer and barrier metal layer are polished away using chemical mechanical polishing (CMP) with a polish stop at the silicon nitride layer. The metal layer forms a metal plug. The silicon nitride layer prevents erosion of the oxide layer during the polishing step to complete formation of a metal plug in the fabrication of an integrated circuit device.

Method for improving oxide erosion of tungsten CMP operations

A new method of forming a dual damascene interconnect structure, wherein damage of interconnect and contamination of dielectrics during etching is minimized by having an embedded organic stop layer over the lower interconnect and later etching the organic stop layer with an H2 containing plasma, or hydrogen radical.

Method of manufacturing embedded organic stop layer for dual damascene patterning

Novel low dielectric constant materials for use as dielectric in the dual damascene process are provided. A low dielectric constant material dielectric layer is formed by reacting a nitrogen-containing precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, novel low dielectric constant materials for use as a passivation or etch stop layer in the dual damascene process are provided. A carbon-doped silicon nitride passivation or etch stop layer having a low dielectric constraint is formed by reacting a substituted ammonia precursor and a substituted organosilane in a plasma-enhanced chemical deposition chamber. Alternatively, a silicon-carbide passivation or etch stop layer having a low dielectric constant is formed by reacting a substituted organosilane in a plasma-enhanced chemical deposition chamber. Also, an integrated process of forming passivation, dielectric, and etch stop layers for use in the dual damascene process is described.

Low dielectric constant materials for copper damascene

A method of preventing metal penetration and diffusion from metal structures formed over a semiconductor structure, comprising the following steps. A semiconductor structure including a patterned dielectric layer is provided. The patterned dielectric layer includes an opening and an upper surface. The dielectric layer surface is then passivated to form a passivation layer. A metal plug is formed within the dielectric layer opening. The passivation layer prevents penetration and diffusion of metal out from the metal plug into the semiconductor structure and the patterned dielectric layer.

Growing community of inventors

Singapore, Singapore

Yi Liang Xu