Richtek Technology Corporation

Novatek Microelectronics Corp.

Other

Yi-Kuang Chen

Ming-Jun Hsiao

A half-bridge driver drives a half-bridge circuit. The half-bridge driver includes a switch selection circuit and at least one slew rate adjustment circuit, wherein the slew rate adjustment circuit includes a pulse-width control unit, an adjustment pulling unit and a halt adjustment pulling unit. The switch selection circuit generates a source current or a sink current to correspondingly pull up or pull down the gate-source voltage of the upper switch or the lower switch, thereby turning-on or turning-off the upper switch or the lower switch. The adjustment pulling unit is for adjusting the pulling-up or pulling-down of the gate-source voltage of the upper switch or the lower switch. The stop-adjustment pulling unit is for stopping adjusting the pulling-up or pulling-down of the gate-source voltage of the upper switch or the lower switch.

Half-bridge driver and half-bridge driving method having slew rate adjustment function

A BD type pulse width modulation (PWM) circuit is configured to convert a pair of complementary input signals to a pair of output PWM signals. The BD PWM circuit modulates a basic modulation signal according to the pair of input signals, to generate a basic PWM signal. The common mode levels of the pair of input signals and the basic modulation signal are the same. The BD PWM circuit modulates an offset modulation signal according to the pair of input signals to generate an offset PWM signal. The offset modulation signal and the basic modulation signal have a non-zero offset in between. The BD PWM circuit selects the offset PWM signal or a heavy load PWM signal as the pair of output PWM signals. The heavy load PWM signal is correlated with the basic PWM signal.

BD PWM modulation circuit for use in class D amplifier and modulation method thereof

A pulse width modulation (PWM) method for converting an input signal into an output PWM signal includes the following steps: generating a first linear periodic wave and a second linear periodic wave which are triangle waves or sawtooth waves, wherein the amplitude of the first linear periodic wave is greater than the amplitude of the second linear periodic wave; determining whether the level of the input signal is lower than a light load threshold; when the level of the input signal is lower than the light load threshold, generating the output PWM signal according to a comparison between the input signal and the second linear periodic wave; and when the level of the input signal is higher than the light load threshold, generating the output PWM signal according to a comparison between the input signal and the first linear periodic wave.

Pulse width modulation method

A class-D amplifying system includes: a first digital-to-analog converter (DAC), a class-D amplifier circuit and a second DAC. The first DAC generates an analog input signal according to a digital input signal. The class-D amplifier circuit generates an output signal according to the analog input signal in a pulse width modulation (PWM) manner. The second DAC generates a common mode (CM) adjustment current for adjusting a CM voltage of the analog input signal according to one or more of the following parameters: (1) the CM voltage of the analog input signal; and/or (2) a driving power. A power stage circuit of the class-D amplifier circuit is powered by the driving power. The second DAC determines which parameter the CM adjustment current is correlated to according to: (A) A level state of the output signal; and/or (B) A level state of a PWM signal of the class-D amplifier circuit.

Class-D amplifying system and class-D amplifier circuit

A low distortion triangular wave generator circuit generates a triangular wave signal by performing integration on an integration capacitor via a charging current and a discharging current during a charging period and a discharging period within a switching period of an external clock signal. A time length of the charging period is identical to a time length of the discharging period. A common mode related signal related to a common mode characteristic of the triangular wave signal is generated. An adjusting signal is generated according to a difference between the common mode related signal and a predetermined DC (direct current) level. The adjusting signal adjusts at least one of the charging current and the discharging current via feedback mechanism such that the triangular wave signal is a symmetrical triangular wave, and an average voltage of the triangular wave signal is equal to a target DC level.

Low distortion triangular wave generator circuit and low distortion triangular wave generation method

A switching converter includes an input end, N output ends, an inductor, a charging/discharging control unit, an energy distribution control unit and a logic control unit. The input end is utilized for receiving an input voltage. The N output ends are utilized for outputting N output voltages. The inductor is utilized for storing energy of the input voltage. The charging/discharging control unit and the energy distribution control unit are respectively utilized for generating a charging/discharging control signal and N energy distribution control signals to control a charging switch and N output switches according to the N output voltages, wherein the i-th distribution control signal is corresponding to the i-th output voltage signal to the N-th output voltage signal. The logic control unit is utilized for generating the charging switch control signal and N output switch control signals according to the charging/discharging control signal and the N energy distribution control signals.

Switching converter and control method

A multiphase clock divider includes: a reference clock generator for generating a plurality of reference clocks; and at least one output clock generator including a first multiplexer for selecting to output a selected reference clock, a second multiplexer for selecting to output a first selected input clock, a third multiplexer for selecting to output a second selected input clock, a first flip-flop for outputting a first sampling clock according to the selected reference clock and the first selected input clock, a second flip-flop for outputting a second sampling clock according to the first sampling clock and the second selected input clock, and a fourth multiplexer for selecting to output the first sampling clock or the second sampling clock to generate an output clock.

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Taichung, Taiwan

Yi-Kuang Chen