Samsung Electronics Co., Ltd.

Yi-Koan Hong

Byung-Lyul Park

Nae-in Lee

Ho-jin Lee

Kwang-Jin Moon

Joo-Hee Jang

Si-Young Choi

Pil-Kyu Kang

Tae-Hyun Kim

Kyung-Hyun Kim

Suk-Hun Choi

Ji-soon Park

Kyu-ha Lee

Tae-Yeong Kim

Seok-Ho Kim

Kyung-tae Nam

Jin-Ho An

Yeun-Sang Park

Jun-ho Jeong

Jum-yong Park

Hyo-Ju Kim

Ki-Ho Bae

A semiconductor device includes a first conductive pattern at an upper portion of a first insulating interlayer on a first substrate, a first plurality of conductive nanotubes (CNTs) extending vertically, a second conductive pattern at a lower portion of a second insulating interlayer beneath a second substrate, and a second plurality of CNTs extending vertically. A lower surface of the second insulating interlayer contacts an upper surface of the first insulating interlayer. At least a portion of a sidewall of each of the first plurality of CNTs is covered by the first conductive pattern, and at least a portion of a sidewall of each of the second plurality of CNTs is covered by the second conductive pattern. The first and second conductive patterns vertically face each other, and at least one of the first plurality of CNTs and at least one of the second plurality of CNTs contact each other.

Semiconductor devices

A first insulating layer is formed on a substrate. An opening is formed in the first insulating layer. A barrier layer is formed on the first insulating layer and conforming to sidewalls of the first insulating layer in the opening, and a conductive layer is formed on the barrier layer. Chemical mechanical polishing is performed to expose the first insulating layer and leave a barrier layer pattern in the opening and a conductive layer pattern on the barrier layer pattern in the opening, wherein a portion of the conductive layer pattern protrudes above an upper surface of the insulating layer and an upper surface of the barrier layer pattern. A second insulating layer is formed on the first insulating layer, the barrier layer pattern and the conductive layer pattern and planarized to expose the conductive layer pattern. A second substrate may be bonded to the exposed conductive layer pattern.

Method of fabricating multi-substrate semiconductor devices

In a method for fabricating a semiconductor, a first conductive pattern structure partially protruding upwardly from first insulating interlayer is formed in first insulating interlayer. A first bonding insulation layer pattern covering the protruding portion of first conductive pattern structure is formed on first insulating interlayer. A first adhesive pattern containing a polymer is formed on first bonding insulation layer pattern to fill a first recess formed on first bonding insulation layer pattern. A second bonding insulation layer pattern covering the protruding portion of second conductive pattern structure is formed on second insulating interlayer. A second adhesive pattern containing a polymer is formed on second bonding insulation layer pattern to fill a second recess formed on second bonding insulation layer pattern. The first and second adhesive patterns are melted. The first and second substrates are bonded with each other so that the conductive pattern structures contact each other.

Methods of manufacturing a semiconductor device

Provided is a semiconductor device. The semiconductor device includes a passivation layer defining a metal pattern on a first surface of a substrate, an inter-layer insulating layer disposed on a second surface of the substrate, and a piezoelectric pattern formed between the metal pattern and the passivation layer on the first surface of the substrate. A through-silicon-via and/or a pad can be directly bonded to another through-silicon-via and/or another pad by applying pressure only, and without performing a heat process.

Semiconductor device having metal patterns and piezoelectric patterns

A semiconductor device includes an interlayer insulating layer disposed on a substrate, the interlayer insulating layer comprising an opening exposing the substrate, a barrier layer pattern disposed within the opening, and a conductive pattern disposed on the barrier layer pattern, the conductive pattern having an oxidized portion extending out of the opening and a non-oxidized portion within the opening, wherein a width of the conductive pattern is determined by a thickness of the barrier layer pattern.

Semiconductor device having a conductive structure including oxide and non oxide portions

Growing community of inventors

Suwon-si, South Korea

Yi-Koan Hong