Lextar Electronics Corporation

Yi-Jyun Chen

Chih-Hao Lin

Shiou-Yi Kuo

Yu-Chun Lee

Li-Cheng Yang

Hsin-Lun Su

Fang-Chang Hsueh

A pixel structure includes a light emitting diode chip and a light blocking structure. The light emitting diode chip includes a P-type semiconductor layer, an active layer, an N-type semiconductor layer, a first electrode, and K second electrodes. The active layer is located on the P-type semiconductor layer. The N-type semiconductor layer is located on the active layer. The N-type semiconductor layer has a first top surface that is distant from the active layer. The first electrode is electrically connected to the P-type semiconductor layer. The light blocking structure is located in the light emitting diode chip and defines K sub-pixel regions. The active layer and the N-type semiconductor layer are divided into K sub-portions respectively corresponding to the K sub-pixel regions by the light blocking structure. The K sub-pixel regions share the P-type semiconductor layer.

Pixel structure

An LED chip package includes a substrate having a metal terminal (gold finger structure). A LED chip set is composed of a plurality of LED chips formed in one piece, and has a plurality of light-emitting areas which are separated from each other. The LED chip set is disposed on the substrate and electrically connected to the metal terminal.

LED chip package

A light-emitting diode chip package is provided. The light-emitting diode chip package includes a substrate; a light-emitting diode chip set (LED chip set) disposed over the substrate, wherein the LED chip set is formed by a plurality of light-emitting diode chips (LED chips) in one piece; and at least two electrodes disposed over the substrate and electrically connected to the LED chip set.

Light-emitting diode chip package

The present invention provides a eutectic solder structure for a chip including a substrate and a solder structure on the substrate. The solder structure includes an alternate lamination of a plurality of first metal layers and a plurality of second metal layers, wherein each second metal layer has a continuous region and a plurality of openings and the melting point of the plurality of second metal layers is higher than that of the plurality of first metal layers. The eutectic solder structure for a chip also includes a chip on the solder structure, wherein the chip is bonded to the substrate by a eutectic reaction of the solder structure.

Eutectic solder structure for chip

A semiconductor chip structure including a semiconductor chip having a pair of electrodes is disclosed. The electrodes have different conductivity types for electrical connection, respectively. A thermoelectric cooling material layer is disposed within each of the pair of electrodes, respectively.

Growing community of inventors

Chiayi County, Taiwan

Yi-Jyun Chen