Taiwan Semiconductor Manufacturing Comp. Ltd.

Nan Ya Technology Corporation

National Applied Research Laboratories

Au Optronics Corporation

Tsinghua University

Medivisiontech Co., Ltd

Yi-Ju Chen

Jui-Hsiu Jao

Jyh-Huei Chen

Kuo-Chiang Tsai

Fu-Hsiang Su

Hsin-Yi Tsai

Kuo-Cheng Huang

Shih-Lien Linus Lu

Cheng Hung Lee

Meng-Fan Chang

Li-Yi Chen

Ru-Shang Hsiao

Jui-Che Tsai

Jhen-Yu Tsai

Po-Lun Chen

Chin-Ling Huang

Chia-Yu Lee

I-Shan Huang

Ke-Jing Yu

Sheng-Fu Yu

Ching-Ching Yang

Han-Chao Chang

Kuan Yu Chen

Chieh-Ting Chen

Chiao-Hsiung Chuang

Chien-Cheng Chen

Kuo-Rung Hsiao

Cheng-Han Yang

Shuo-Huei Lin

Ruenn-Sheng Peng

A semiconductor wafer, a benchmark device embedded on a semiconductor wafer, and a method of operating a benchmark device embedded on a semiconductor wafer are provided. The semiconductor wafer includes a benchmark device disposed within a scribe line of the semiconductor wafer. The benchmark device includes a transistor, a diode, and a disconnecting switch electrically connected to the transistor and the diode. The disconnecting switch is configured to form a conductive path between the transistor and the diode at a first stage, and to electrically isolate the transistor from the diode at a second stage.

Benchmark device on a semiconductor wafer with fuse element

A method includes receiving a semiconductor structure having a source contact feature electrically connected to a source feature and a drain contact feature electrically connected to a drain feature. The method includes etching to form a drain via trench over the drain contact feature and forming a drain via in the drain via trench. After forming the drain via, the method further includes etching to form a source via trench over the source contact feature and forming a source via in the source via trench. The drain via has a first dimension along a first direction, the source via has a second dimension along the first direction, and the second dimension is greater than the first dimension.

Methods of manufacturing via structures on source/drain contacts

A semiconductor device structure is provided. The semiconductor device structure includes a conductive gate stack formed over a substrate. A gate dielectric layer covers opposite sidewalls and a bottom of the conductive gate stack. A first gate spacer layer and a second gate spacer layer respectively cover portions of the gate dielectric layer corresponding to the opposite sidewalls of the conductive gate stack. A source/drain contact structure is separated from the conductive gate stack by the gate dielectric layer and the first gate spacer layer. A first insulating capping feature covers the conductive gate stack and is separated from the second gate spacer layer by the gate dielectric layer, and a second insulating capping feature covers the source/drain contact structure. An upper surface of the second insulating capping feature is substantially level with an upper surface of the first insulating capping feature.

Contact structure with insulating cap

A method for activating a backup unit includes providing a fuse element connected to the backup unit. The fuse element includes an active area, which includes a source region and a drain region beside the source region, a gate region disposed on the active area, and a shallow trench isolation (STI) structure surrounding the active area. The method also includes applying a stress voltage on the drain region of the fuse element; accumulating electrons in a portion of the STI structure adjacent to the drain region; generating a conductive path through the drain region and the source region so that the fuse element is conductive; and activating the backup unit through the fuse element.

Method for activating backup unit through fuse element

The present disclosure provides a method of operating a benchmark device embedded on a semiconductor wafer. The method includes applying a first voltage to a first electrode of the benchmark device, and applying a second voltage to a second electrode of the benchmark device. The method further includes electrically isolating a first component of the benchmark device from a second component of the benchmark device through a disconnecting switch connected between the first component and the second component.

Method for operating a benchmark device on a semiconductor wafer with fuse element

A fuse element, a semiconductor device, and a method for activating a backup unit are provided. The fuse element includes an active area, which includes a source region and a drain region beside the source region, a gate region disposed on the active area, and a shallow trench isolation (STI) structure surrounding the active area. In addition, the drain region includes a terminal configured to receive a stress voltage, such that a conductive path is established through the drain region to the source region.

Fuse elements and semiconductor devices

A probe apparatus includes a chuck configured to support a wafer, a track surrounding the chuck, a tester disposed on the track and having a probe. The tester is configured to move around the wafer along a circumferential direction. The probe apparatus also includes a processing unit in communication with the tester and configured to control a movement of the tester.

Probe apparatus with a track

A probe apparatus and a wafer inspection method are provided. The probe apparatus includes a chuck configured to support a wafer, a track surrounding the chuck, a tester disposed on the track and having a probe, and a processing unit in communication with the tester and configured to move the tester circumferentially around the wafer such that the probe is moved from a first portion on the wafer to a second portion on the wafer.

Probe apparatus having a track and wafer inspection method using the same

An exemplary semiconductor device includes a source feature and a drain feature disposed over a substrate. The semiconductor device further includes a source via electrically coupled to the source feature, and a drain via electrically coupled to the drain feature. The source via has a first size; the drain via has a second size; and the first size is greater than the second size. The semiconductor device may further include a first metal line electrically coupled to the source via and a second metal line electrically coupled to the drain via. The source via has a first dimension matching a dimension of the first metal line, and the drain via has a second dimension matching a dimension of the second metal line. The first metal line may be wider than the second metal line.

Semiconductor device with source and drain vias having different sizes

The present application provides a method for preparing a memory device. The method includes: forming an active region in a substrate, wherein the active region has a linear top view shape; forming a gate structure on the substrate, wherein the gate structure has a linear portion intersected with a section of the active region away from end portions of the active region; forming a first insulating layer and a second insulating layer on the substrate, wherein the first insulating layer laterally surrounds the gate structure, and is covered by the second insulating layer; forming an opening penetrating through the first and second insulating layers and exposing a portion of the active region, wherein the opening is laterally spaced apart from the gate structure; and sequentially forming a dielectric layer and an electrode in the opening.

Method for preparing a memory device

An upper gastrointestinal bleeding monitoring system includes a detection device and a signal processing device to determine bleeding condition of an upper gastrointestinal tract by using relation of time and intensity ratios of RGB three primary colors. The detecting device is placed to the upper gastrointestinal tract of a patient via his/her mouth or nasal passage and then stay the upper gastrointestinal tract for several days for detection of bleeding. The signal processing device may receive and display signal from the detection device to help medical professionals check if bleeding occurs in an upper gastrointestinal tract. Moreover, a procedure of determination of bleeding in an upper gastrointestinal tract with the upper gastrointestinal bleeding monitoring system is described.

Upper gastrointestinal bleeding monitoring system

A source/drain region is disposed in a substrate. A gate structure is disposed over the substrate. A gate spacer is disposed on a sidewall of the gate structure. The gate spacer and the gate structure have substantially similar heights. A via is disposed over and electrically coupled to: the source/drain region or the gate structure. A mask layer is disposed over the gate spacer. The mask layer has a greater dielectric constant than the gate spacer. A first side of the mask layer is disposed adjacent to the via. A dielectric layer is disposed on a second side of the mask layer, wherein the mask layer is disposed between the dielectric layer and the via.

Using mask layers to facilitate the formation of self-aligned contacts and vias

A semiconductor device structure is provided. The semiconductor device structure includes a gate stack formed over a semiconductor substrate, a source/drain contact structure adjacent to the gate stack, and a gate spacer formed between the gate stack and the source/drain contact structure. The semiconductor device structure also includes a first insulating capping feature covering an upper surface of the gate stack, a second insulating capping feature covering an upper surface of the source/drain contact structure, and an insulating layer covering the upper surfaces of the first insulating capping feature and the second insulating capping feature. The second insulating capping feature includes a material that is different from a material of the first insulating capping feature. The semiconductor device structure also includes a via structure passing through the insulating layer and the first insulating capping feature and electrically connected to the gate stack.

A memory storage device is fabricated using a semiconductor fabrication process. Often times, manufacturing variations and/or misalignment tolerances present within the semiconductor fabrication process can cause the memory storage device to differ from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process. For example, uncontrollable random physical processes in the semiconductor fabrication process can cause small differences, such as differences in doping concentrations, oxide thicknesses, channel lengths, structural widths, and/or parasitics to provide some examples, between these memory storage devices. These small differences can cause bitlines within the memory storage device to be physically unique with no two bitlines being identical. As a result, the uncontrollable random physical processes in the semiconductor fabrication process can cause electronic data read from the memory storage device to propagate along the bitlines at different rates. This physical uniqueness of the bitlines can be utilized to implement a physical unclonable function (PUF) allowing the memory storage device to be differentiated from other memory storage devices similarly designed and fabricated by the semiconductor fabrication process.

Balanced coupling structure for physically unclonable function (PUF) application

A write assist circuit includes a write detection circuit, a write detection-aware write driver and a write condition recovery circuit. The write detection circuit receives a detected result signal and a write data, and generates a write detect control signal and generating a selecting signal according to the detection result signal and the write data. The write detection-aware write driver receives the write detect control signal and operates a write detection operation on a selected memory cell according to the write detect control signal, and decides whether to provide a negative voltage to one of a bit line and an inverted bit line of the selected memory cell or not according to the selecting signal. The write condition recovery circuit respectively couples the bit line and the inverted bit line to the write data line and the inverted data line according to a write pass-gate control signal, and provides a pre-charge voltage to the write data line and the inverted data line during the write detection time period according to a recovery signal.

Growing community of inventors

Tainan, Taiwan

Yi-Ju Chen