Taiwan Semiconductor Manufacturing Comp. Ltd.

Dynavax Technologies Corporation

Medigen Vaccine Biologics Corporation

Yi-Jiun Lin

Wen-Ting Chu

Kuo-Chi Tu

Chia-Ta Hsieh

Hung-Cheng Sung

Feng-Jia Shiu

Chi-Hsin Lo

Shih-Wei Wang

Ching-Sen Kuo

Hsiang-Fan Lee

Robert L Coffman

Yu-Chi Wu

Charles Chen

Chia-Tong Ho

Yi-Shing Chang

Chung-Chin Wu

Robert S Janssen

David Novack

Kuo-Wei Chu

John Darren Campbell

Tsun-Yung Kuo

Meei-Yun Lin

Paula Traquina

The present invention relates to an immunogenic composition against severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2), especially to an immunogenic composition having a recombinant SARS-CoV-2 S protein and adjuvant.

Immunogenic composition against severe acute respiratory syndrome coronavirus 2 (SARS-CoV-2)

A method for forming triple polysilicon split gate electrodes in a EEPROM flash memory array providing a first gate structure; blanket depositing a first polysilicon layer over the first gate structure; etching back the first polysilicon layer according to a first dry etching process; blanket depositing a second dielectric insulating layer over the first polysilicon layer; blanket depositing a second polysilicon layer over the second dielectric insulating layer; and, lithographically patterning and dry etching according to a respective third and fourth dry etching process through a thickness portion of the respective second and first polysilicon layers to respectively form third and second polysilicon gate electrodes.

Poly-etching method for split gate flash memory cell

A split gate flash memory cell structure is disclosed for prevention of reverse tunneling. A gate insulator layer is formed over a semiconductor surface and a floating gate is disposed over the gate insulator layer. A floating gate insulator layer is disposed over the floating gate and sidewall insulator spacers are disposed along bottom portions of the floating gate sidewall adjacent to said gate insulator layer. The sidewall insulator spacers are formed from a spacer insulator layer that had been deposited in a manner that constitutes a minimal expenditure of an available thermal budget and etching processes used in fashioning the sidewall insulator spacers etch the spacer insulator layer faster than the gate insulator layer and the floating gate insulator layer. An intergate insulator layer is disposed over exposed portions of the gate insulator layer, the floating gate, the floating gate insulator layer and the sidewall insulator spacers. A conductive control gate is disposed over the intergate insulator layer, covering about half of the floating gate.

Space process to prevent the reverse tunneling in split gate flash

A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.

Method to make minimal spacing between floating gates in split gate flash

Growing community of inventors

Taipei, Taiwan

Yi-Jiun Lin