Taiwan Semiconductor Manufacturing Comp. Ltd.

Au Optronics Corporation

Lite-on Technology Corporation

Yi-Jen Chen

Che-Cheng Chang

Chih-Teng Liao

Chang-Yin Chen

Yung-Jung Chang

Jie-Cheng Deng

Chun-Sheng Liang

Shih-Hsun Chang

Yung Jung Chang

Wei-Kai Huang

Horng-Huei Tseng

Shu-Hui Wang

Jui Fu Hsieh

Chiung-Pin Wang

Chia-Chun Liao

Yu-Ling Ko

Chia-Chi Yu

Harry-Hak-Lay Chuang

Ming Zhu

Yi-Ren Chen

Yu-Li Lin

Chen-Shun Tsai

Sheng-Chi Shih

Bo-Feng Young

Jr-Jung Lin

Tung-Wen Cheng

Hsin-Che Chiang

Kun-Yu Lin

Chai-Wei Chang

Tzu-Chan Weng

Chih-Shan Chen

An Chyi Wei

Che-fu Chen

Ming-Jhe Sie

Hsiu-Hao Tsao

Yi-Chung Lee

Chia-Yang Liao

Hsu Ming Hsiao

Hong Pin Lin

En-Ping Lin

Guey-Shyung Cho

Chi-Sian Chuang

I-Chung Wang

Sheng-Kai Jou

Tzu-Chieh Lai

I-Chen Chen

Chih-Han Lin

Ya-Ling Hsu

Yi-Pai Huang

Peng-Bo Xi

Shin-Hung Yeh

Yen-Chung Chen

Cheng-Han Tsao

Jen-Hsiang Lu

Ming-Chou Wu

Chia-Cheng Tai

Chao-Po Lu

Chin-Tsai Chen

Shih-Chiang Lu

Jui Fu Hseih

Young Liao

Yun-Tzuo Lai

Ching-Chi Tsai

Tsukada Kazunori

Hsi-Shen Chuang

Pu-Fan Chen

A semiconductor structure includes a first fin, a second fin, a first gate, a second gate, at least one spacer, and an insulating structure. The first gate is present on the first fin. The second gate is present on the second fin. The spacer is present on at least one side wall of at least one of the first gate and the second gate. The insulating structure is present between the first fin and the second fin, in which the spacer is substantially absent between the insulating structure and said at least one of the first gate and the second gate.

Semiconductor structure and manufacturing method thereof

In a method, a first dielectric layer is formed over semiconductor fins, a second dielectric layer is formed over the first dielectric layer, the second dielectric layer is recessed below a top of each of the semiconductor fins, a third dielectric layer is formed over the recessed second dielectric layer, and the third dielectric layer is recessed below the top of the semiconductor fin, thereby forming a wall fin. The wall fin includes the recessed third dielectric layer and the recessed second dielectric layer disposed over the recessed third dielectric layer. The first dielectric layer is recessed below a top of the wall fin, a fin liner layer is formed, the fin liner layer is recessed and the semiconductor fins are recessed, and source/drain epitaxial layers are formed over the recessed semiconductor fins, respectively. The source/drain epitaxial layers are separated by the wall fin from each other.

Method of manufacturing a semiconductor device and a semiconductor device

A method includes determining a target etching depth for etching a plurality of dielectric regions in a wafer. The wafer includes a plurality of protruding semiconductor fins and the plurality of dielectric regions between the plurality of protruding semiconductor fins. The method further includes etching the plurality of dielectric regions, projecting a light beam on the wafer, and generating a spectrum from a reflected light reflected from the wafer, determining an end point for etching based on the spectrum. The end point is an expected time point. The plurality of dielectric regions are etched to the target etching depth. The etching of the plurality of dielectric regions is stopped at the end point.

End point control in etching processes

In a method of manufacturing a semiconductor device, a mask pattern is formed over a target layer to be etched, and the target layer is etched by using the mask pattern as an etching mask. The etching is performed by using an electron cyclotron resonance (ECR) plasma etching apparatus, the ECR plasma etching apparatus includes one or more coils, and a plasma condition of the ECR plasma etching is changed during the etching the target layer by changing an input current to the one or more coils.

Method of manufacturing a semiconductor device

In a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. Each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom.

Method of manufacturing semiconductor devices and semiconductor device

A method, for making a semiconductor device, includes forming a first fin over a substrate. The method includes forming a dummy gate stack on the first fin. The method includes forming a first gate spacer along a side of the dummy gate stack. The first gate spacer includes a first dielectric material. The method includes forming a second gate spacer along a side of the first gate spacer. The second gate spacer includes a semiconductor material. The method includes forming a source/drain region in the first fin adjacent the second gate spacer. The method includes removing at least a portion of the second gate spacer to form a void extending between the first gate spacer and the source/drain region.

Fin field-effect transistor with void and method of forming the same

In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma process comprises applying pulsed bias voltage and RF voltage with pulsed power.

In a method of manufacturing a semiconductor device including a Fin FET, a fin structure extending in a first direction is formed over a substrate. An isolation insulating layer is formed over the substrate so that an upper portion of the fin structure is exposed from the isolation insulating layer. A gate structure extending in a second direction crossing the first direction is formed over a part of the fin structure. A fin mask layer is formed on sidewalls of a source/drain region of the fin structure. The source/drain region of the fin structure is recessed by a plasma etching process. An epitaxial source/drain structure is formed over the recessed fin structure. In the recessing the source/drain region of the fin structure, the plasma etching process comprises applying pulsed bias voltage and RF voltage with pulsed power.

A semiconductor device manufacturing method includes forming fins in first and second regions defined on a substrate. The fins include first fin, second fin, third fin, and fourth fin. A dielectric layer is formed over fins and a work function adjustment layer is formed over dielectric layer. A hard mask is formed covering third and fourth fins. A first conductive material layer is formed over first fin and not over second fin. A second conductive material layer is formed over first and second fins. A first metal gate electrode fill material is formed over first and second fins. The hard mask covering third and fourth fins is removed. A third conductive material layer is formed over third fin and not over fourth fin. A fourth conductive material layer is formed over third and fourth fins, and a second metal gate electrode fill material is formed over third and fourth fins.

Semiconductor device and manufacturing method thereof

A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a first gate electrode over the semiconductor substrate. The semiconductor device also includes a first gate dielectric layer between the first gate electrode and the semiconductor substrate. The semiconductor device further includes a second gate electrode over the semiconductor substrate. The second gate electrode has an upper portion and a lower portion between the upper portion and the semiconductor substrate, and the upper portion is wider than the lower portion. In addition, the semiconductor device includes a second gate dielectric layer between the second gate electrode and the semiconductor substrate.

Structure and formation method of semiconductor device with gate stack

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Hsinchu, Taiwan

Yi-Jen Chen