Qualcomm Incorporated

Yi-Hung Tseng

Charles James Persico

Marzio Pedrali-Noy

Philip Michael Clovis

Xuhao Huang

Sushma Chilukuri

Mustafa Keskin

Karthik Nagarajan

An apparatus is disclosed for making circuitry with passive fundamental components more robust. In example implementations, an apparatus includes at least one passive fundamental component and at least one redundant passive fundamental component. The apparatus also includes fault tolerant circuitry coupled to the at least one passive fundamental component and the at least one redundant passive fundamental component. The fault tolerant circuitry includes fault detection circuitry configured to detect a fault of the at least one passive fundamental component. The fault tolerant circuitry also includes component repair circuitry configured to disconnect the at least one passive fundamental component based on the fault.

Robust circuitry for passive fundamental components

An apparatus is disclosed for robust transistor circuitry. In example implementations, an apparatus includes a current mirror and fault handler circuitry that is coupled to the current mirror. The current mirror includes a core transistor having a control terminal, a first transistor, and a second transistor. The first transistor has a control terminal that is coupled to the control terminal of the core transistor. The second transistor has a control terminal that is coupled to the control terminal of the core transistor. The fault handler circuitry is configured to select the first transistor or the second transistor to provide a mirrored current of the current mirror.

Robust transistor circuitry

A digital to analog converter (DAC) includes a plurality of DAC transistor devices having an input side configured to be selectively coupled to a system voltage based on a digital input signal and an output side configured to provide an analog output signal, a plurality of non-DAC transistor devices coupled to the input side of the DAC transistor devices, the non-DAC transistor devices configured as variable resistances, and a control circuit configured to adjust a bias of the non-DAC transistor devices.

Digital-to-analog converter

Certain aspects of the present disclosure are directed to a digitally controlled oscillator (DCO). The DCO generally includes an oscillator, a current mirror having a first branch coupled to a control input of the oscillator, a first current source, and a first transistor having a drain coupled to the first current source and a gate of the first transistor, a source of the first transistor being coupled to the control input of the oscillator. The DCO may also include a second current source coupled to the source of the first transistor, and a second transistor having a gate coupled to the gate of the first transistor, a drain of the second transistor being coupled to a second branch of the current mirror.

Self-biased digitally controlled oscillator architecture

Certain aspects of the present disclosure provide digital-to-analog converters (DACs). One example DAC generally includes a first transistor configured to selectively couple a power source to a load. In a first mode of operation of the DAC, the first transistor is closed and couples the load to the power source. In a second mode of operation of the DAC, the first transistor is open and decouples the load from the power source. The DAC further includes a current limiting circuit selectively coupled between the first transistor and a reference voltage. In the first mode, the current limiting circuit is decoupled from the reference voltage. In the second mode, the current limiting circuit is coupled to the reference voltage.

A memory controller is provided that drives data and a corresponding first data strobe to a plurality of endpoints. Each endpoint is configured to register the received data from the memory controller responsive to the first data strobe and then to re-register the received data responsive to a second data strobe. A clock synchronization circuit functions to keep the received first data strobe at one of the endpoints sufficiently synchronous with the second data strobe.

Distributed clock synchronization

A clock synchronization circuit includes a multi-phase clock generator to generate a plurality of delayed clocks, each delayed clock having a unique delay with regard to a source clock. The clock synchronization circuit further includes a selection circuit that selects one of the delayed clocks according to a phase error to form a local clock driven into a local clock path and received at the clock synchronization circuit as a received local clock. The selection circuit determines the phase error by comparing the received local clock to a reference clock.

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San Diego, CA, United States of America

Yi-Hung Tseng