Semiconductor Manufacturing International (shanghai) Corporation

Semiconductor Manufacturing International (beijing) Corporation

Covestro Deutschland Ag

Bayer Materialscience Ag

Tongji University

Shanghai Tobacco Group Co., Ltd.

Yi Hua Shen

Xi Lin

Jian Pan

Hui Zhao

Chao Chen

Hartmut Nefzger

Jing Yang

Wolfgang Kaufhold

Tong Zhang

Wolfgang Bräuer

Chenxi Zhang

Hao Zhong

Zhiguo Yan

Wenqi Ding

Hehua Zhu

Saijing Zheng

Yun Chu Yu

Sen Sheng Li

Gang Sun

Yichun Zhang

Yihan Gao

Aiqun Zheng

The present disclosure provides a fire test system and method for tunnel structure based on real-time fusion of numerical and physical spaces. The fire test system includes: a physical test unit, to perform a holographic fire test on the typical segment components of tunnel structure system in a physical space, to obtain holographic characteristic parameter data of the typical components; a numerical analysis unit, to establish a full-scale numerical model of the tunnel-stratum composite system in a numerical space, to obtain multi-field coupling boundary data of the typical components; and a fusion control unit, to control and adjust a multi-field coupling boundary of the physical space according to the multi-field coupling boundary data, and to update and adjust an input parameter of the numerical space according to the holographic characteristic parameter data.

Fire test system and method for tunnel structure based on real-time fusion of numerical and physical spaces

A field-effect-transistor includes forming a fin structure on a substrate, a gate structure formed across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, a first doped layer, made of a first semiconductor material and doped with first doping ions, in each fin structure on one side of the corresponding gate structure, and a second doped layer, made of a second semiconductor material, doped with second doping ions, and having doping properties different from the first doped layer, in each fin structure on another side of the corresponding gate structure.

Field-effect-transistors

A self-heating effect apparatus includes a memory and a processor. The processor is coupled to the memory and configured to process a self-heating effect model for characterizing a heat flow network of devices. The devices include a device under test and one or more adjacent devices surrounding the device under test. The self-heating effect model includes a reference thermal resistance and a reference thermal capacity; a thermal temperature feedback model used to acquire a thermal level of the device under test; a thermal resistance modification model used to acquire a modified thermal resistance of the device under test according to the thermal level of the device under test and the reference thermal resistance; and a thermal capacity modification model used to acquire a modified thermal capacity of the device under test according to the thermal level of the device under test and the reference thermal capacity.

Self-heating effect apparatus and test method

A dynamic random access memory (DRAM) is provided and includes a base substrate. The base substrate includes a semiconductor substrate, a plurality of fins formed on the semiconductor substrate, and an isolation structure formed on the semiconductor substrate and covering portions of side surfaces of the plurality of fins. The dynamic random access memory further includes an interlayer dielectric layer formed over the base substrate and covering top surfaces of the plurality of fins and the isolation structure; and a memory structure, formed in an opening passing through the interlayer dielectric layer and each of the plurality of fins, the opening extending to and exposing a top surface of a portion of the isolation structure. The memory structure includes a first conductive layer, a memory medium layer on the first conductive layer, and a second conductive layer on the memory medium layer.

Dynamic random access memory

Dynamic random access memory (DRAM) and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming a gate structure over the base substrate; forming doped source/drain regions in the base substrate at two sides of the gate structure, respectively; forming an interlayer dielectric layer over the gate structure, the base substrate and the doped source/drain regions; forming a first opening, exposing one of the doped source/drain regions at one side of the gate structure, in the interlayer dielectric layer; and forming a memory structure in the first opening and on the one of doped source/drain regions.

Dynamic random access memory and fabrication method thereof

Dynamic random access memory (DRAM) and fabrication methods thereof are provided. An exemplary fabrication method includes providing a base substrate; forming an interlayer dielectric layer over the base substrate; forming an opening passing through the interlayer dielectric layer; and forming a memory structure, having a first conductive layer, a memory medium layer on the first conductive layer, and a second conductive layer on the memory medium layer, in the opening.

The present invention provides a smoking machine for an electronic cigarette, relating to the technical field of electronic cigarettes. The smoking machine for an electronic cigarette comprises: a housing; a rotary disc installed on a side surface of the housing, a central axis of the rotary disc is parallel to a horizontal plane, and the rotary disc rotates relative to the housing with the central axis of the rotary disc as a center, a disc-body smoking through hole is provided on an end face of the rotary disc, a housing sealing member is disposed on a side surface of the housing, a sealing ventilation hole penetrating into the housing in a horizontal direction is provided in the housing sealing member, and an end face of the housing sealing member is in contact with the end face of the rotary disc; and a main control circuit board electrically connected to the rotary disc. The rotary disc of the present invention is perpendicular to a horizontal plane, and the electronic cigarette circumferentially rotates along with the rotary disc in a smoking experiment process, so that tobacco tar in a cigarette cartridge flows and fully immerses the oil guiding cotton, thus ensuring sufficient and steady supply of the tobacco tar to an atomizer, and guaranteeing atomization efficiency, atomization amount, and the stability and accuracy of experiment data.

Smoking machine for electronic cigarette

A method for fabrication a field-effect-transistor includes forming a plurality of fin structures on a substrate, forming a gate structure across each fin structure and covering a portion of top and sidewall surfaces of the fin structure, forming a first doped layer, made of a first semiconductor material and doped with first doping ions, in each fin structure on one side of the corresponding gate structure, and forming a second doped layer, made of a second semiconductor material, doped with second doping ions, and having doping properties different from the first doped layer, in each fin structure on another side of the corresponding gate structure.

Field-effect-transistors and fabrication methods thereof

The present invention relates to homogeneous extruded articles made from thermoplastically processable polyurethanes based on polyester diols formed from succinic acid and 1,3-propanediol.

Homogeneous extruded articles made from thermoplastically processable polyurethanes based on polyester diols formed from succinic acid and 1,3-propanediol

A method for manufacturing an integrated circuit may include the following steps: forming a first transistor, which includes a first active region; forming a second transistor, which includes a second active region; forming a third transistor, which includes a gate electrode that overlaps each of the first active region and the second active region; and providing a predetermined voltage to the gate electrode for turning off the third transistor to isolate the first transistor from the second transistor.

Integrated circuit and related manufacturing method

The present invention relates to a polyurethane ballast layer, the method for preparing the same and a railway comprising the polyurethane ballast layer. The polyurethane ballast layer provided in this invention comprises a polyurethane-filled ballast layer and a polyurethane external protective layer, wherein the polyurethane-filled ballast layer comprises ballasts and polyurethane foam filled in the space among the ballasts. The polyurethane ballast layer provided in this invention can reduce the probability of ballast crashing, shifting and cracking under heavy load, and separate the ballast track from the outside environment to prevent rain, snow and wastes from entering into the internal space of the ballast track bed. Furthermore, the polyurethane ballast layer can keep the polyurethane foam filled in the ballasts layer away from water in the outside environment to avoid hydrolysis. The polyurethane ballast layer presented in this invention can be used in the railway ballast track bed to extend the track bed maintenance cycle, and save maintenance cost significantly.

Growing community of inventors

Shanghai, China

Yi Hua Shen