Faraday Technology Corporation

Yi-Hua Chang

Hung-Yi Chang

Chih-Fu Chien

Chien-Hui Chuang

Chia-Nan Hong

Chin-Yi Chang

A semiconductor device for testing a semiconductor process applied to manufacturing the semiconductor device is disclosed. The semiconductor device includes at least a testing group. The testing group includes a first testing block and a second testing block. The first testing block includes: a first input node; a first output node; a plurality of first selecting nodes; a first reference device, coupled to the first input node and the first output node; and a first target device, coupled to the first selecting nodes and the first output node. The second testing block includes: a second input node; a second output node; a plurality of second selecting nodes; a second reference device, coupled to the second input node and the second output node; and a second target device, coupled to the second selecting nodes and the second output node.

Semiconductor device for testing semiconductor process and method thereof

A power supply clamp circuit for preventing damage to an integrated circuit due to electrostatic discharge. The power supply clamp circuit includes a voltage generator electrically connected to a first node for generating a voltage; a first PMOS transistor having a source electrically connected to the first voltage source, a gate electrically connected to the first node, and a drain electrically connected to a second node; a first NMOS transistor having a drain electrically connected to the second node, a gate electrically connected to the first node, and a source connected to ground; a second NMOS transistor having a drain electrically connected to the first voltage source, a gate electrically connected to the second node, and a source connected to ground; and a second PMOS transistor having a source electrically connected to the second node, a gate and a drain commonly electrically connected to the first node.

Power supply clamp circuit

An electrostatic discharge protection circuit is connected to a bonding pad and a pre-stage driver. The electrostatic discharge protection circuit includes a PMOS transistor and a NMOS transistor and both connect in series. A source/drain region of the PMOS transistor is connected to a system power source, and the gate electrode is connected to a pre-stage drive, and the other source/drain region is connected to a source/drain region of the NMOS transistor, which is also connected to the bonding pad. Another source/drain region of the NMOS transistor is ground. The gate electrode of the NMOS transistor receives an output of the pre-stage driver. Another PMOS transistor is connected to a capacitor and is also connected to the source/drain region of a system power source and the gate electrode of the NMOS transistor.

Electrostatic discharge protection circuit

An electrostatic discharge protective circuit can receive a pre-stage driver output and involve a first PMOS transistor, a first NMOS transistor and a second NMOS transistor and all connect in series. More particularly, a source region of the first PMOS transistor connects to a system power source; and a drain region connects to a conductive pad, and a gate receives the pre-stage driver output. A gate of the first NMOS transistor connects to a first node A, a gate of the second NMOS transistor connects to a third node C and a source region connects to a grounded node. The third node C also can receive the pre-stage driver output. There is a first resistor between the first node A and the system power source. There is a second PMOS transistor in between the first node A and the third node C and connect with two source/drain regions. And the substrate of the second PMOS transistor also connects with the first node A. Also, a gate of the second PMOS transistor connects with a second node B. There is a second resistor between the second node B and the system power source, and there is a capacitor between the second node B and the grounded node.

Electrostatic discharge protective circuit

An ESD protection circuit layout. The ESD protection circuit layout has a first ESD protection device, a second ESD protection device, a first CDM ESD protection device, a second CDM ESD protection device, a first charge flow prevention device, a PMOS transistor, an input resistor, an NMOS transistor, a second charge flow prevention device and a substrate resistor. Charges within an integrated circuit device are discharged through a discharging loop comprising of the first CDM ESD protection device and the second CDM ESD protection device. Ultimately, the integrated circuit device is protected against CDM ESD and electrical latch-up within the integrated circuit is also minimized.

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Hsinchu Hsien, Taiwan

Yi-Hua Chang