Broadcom Corporation

Cypress Semiconductor Corporation

Yi-Hsien Hao

Shrjie Tzeng

Johnson Yen

Scott Sterling McDaniel

Paul H Scott

John K Lenell

Andrew M Naylor

A method for communicating data between network devices is disclosed. A transmission signal is sent over a port of one of the network devices, where the port is in communication with other network devices of the network devices. A data frame is also sent over the port. The transmission signal and the data frame are sent for a fixed byte time period and at least one idle pattern is included with the data frame when a time required to send all data present is less than the fixed byte time period.

Across-device communication protocol

Memory structure, and packet-based switch including the memory structure, having Address Resolution Table and Packet Data Buffer table employing a shared memory. Transmit Descriptor Table also may share memory. Address Resolution Table can be implemented with direct mapping, for which destination address key direct-mapped address search may be used. The memory structure and switch implement an IEEE Std. 802.3 communication protocol via multiple ports.

Memory structure for resolving addresses in a packet-based network switch

A network device for managing data flow can have a data port configured to receive data, a plurality of pointers for pointing to the data received, and a queue for queuing the plurality of pointers. The queue can be configured to have at least one dynamic threshold therein. Furthermore, the network device can have a control module configured to adjust the at least one dynamic threshold with respect to the data flow.

Dynamic adjust multicast drop threshold to provide fair handling between multicast and unicast frames

A network switch that includes an address resolution table and a VLAN table. The address resolution table comprises a VLAN identifier (ARL VID) in less significant bits, a MAC address, and an action code, wherein each VLAN identifier in the address resolution table is unique. The VLAN table is used for storing information related to frame forwarding. The VLAN table includes a VLAN identifier (VLAN VID) in more significant bits, a forward map and an un-tag map. The ARL VID is used to access an associated entry in the VLAN table.

Individually programmable most significant bits of VLAN ID

The present invention provides a method of controlling data flow within a network device. The method includes the steps of snooping a data packet before the data packet is stored in a memory buffer of the network device to determine a packet size, aggregating the packet size to generate a total number of data packets within a burst if the packet size exceeds a predetermined packet size. The method also includes the steps of lowering a threshold of the memory buffer to a reset threshold if the total number of data packets exceeds a predetermined number of consecutive data packets and activating a pause frame based upon the reset threshold to temporarily suspend transmission of incoming data packets to the network device.

Adaptive flow control method and apparatus

A network device, which includes a port, a tag generation unit and a flow control module, is provided. The port, which is connected to a network entity, is configured to send and receive a data packet. The tag generation unit is configured to generate a tag based upon the network entity. The tag generation unit is also configured to add the tag to the data packet and to activate the tag. The flow control module is coupled with a buffer, and is configured to control storage of the data packet into the buffer. The flow control module is also coupled with the port, and is configured to control a communication session conducted between the network device and the network entity based upon the tag.

Fairness scheme method and apparatus for pause capable and pause incapable ports

An Asynchronous Transfer Mode ATM receiver is disclosed. The ATM receiver comprises an input that receives an ATM cell. A first-in first-out (FIFO) is coupled to the input. The FIFO stores the ATM cell received from the input. A header error correction (HEC) checking circuit is coupled to the input. The HEC checking circuit starts to check a header in the ATM cell for an error at substantially the same time when the ATM cell is being stored in the FIFO.

Growing community of inventors

Saratoga, CA, United States of America

Yi-Hsien Hao