Mediatek Corporation

Alpha Networks Inc.

Yi-Hsien Cho

Robert Bogdan Staszewski

Yu-Li Hsueh

Jing-Hong Conan Zhan

Ang-Sheng Lin

Chi-Hsueh Wang

Ming-Wang Guo

Chun-Fu Wang

Chien-Kai Kao

Jen-Sheng Huang

Ying-Yung Chen

Shang-I Huang

Yao-Chang Hsieh

Yu-Hsin Lin

Kuan-Hua Chao

Tse-Hsien Yeh

The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR includes a phase detector, a digital loop filter, a first phase interpolator and a second phase interpolator. The PLL is configured to generate a first clock signal with SSC modulation and a control signal. The phase detector is configured to generate a detection result according an input signal and an output clock signal, wherein the input signal is with SSC modulation. The digital loop filter is configured to filter the detection result to generate a filtered signal. The first phase interpolator is configured to generate a second clock signal according to the filtered signal and the first clock signal. The second phase interpolator is configured to cancel an SSC component contributed by the first clock signal in the second clock signal to generate the output clock signal according to the control signal.

Clock and data recovery circuit with spread spectrum clocking synthesizer

The present invention provides a circuitry including a PLL and a CDR circuit, wherein the CDR circuit includes a phase detector, a loop filter, a SSC demodulator, a control code generator and a phase interpolator. The PLL is configured to generate a clock signal with SSC modulation and a SSC direction signal. The phase detector is configured to compare phases of an input signal and an output clock signal to generate a detection result, wherein the input signal is with SSC modulation. The loop filter is configured to filter the detection result to generate a filtered signal. The SSC demodulator is configured to receive the SSC direction signal to generate a control signal. The control code generator is configured to generate a control code according to the filtered signal and the control signal to control the phase interpolator to use the clock signal to generate the output clock signal.

A clock data recovery apparatus includes an oscillator, a sampler circuit, and a frequency control circuit. The oscillator generates a clock signal according to a bias voltage. The sampler circuit samples an input data signal to generate a sampling signal according to the clock signal. The frequency control circuit generates the bias voltage by performing integration calculation, digital-to-analog conversion, and low-pass filtering for the sampling signal.

Clock data recovery apparatus and method capable of reducing more noise as well as tracking larger frequency offsets

An interpolator includes interpolation cells. Each interpolation cell includes a first driving unit and a second driving unit. The first driving unit includes a first pulling-up circuit for selectively coupling an output terminal to a high voltage, a first pulling-down circuit for selectively coupling the output terminal to a low voltage, and a pair of first switches for selectively enabling/disabling the first pulling-up circuit and the first pulling-down circuit. The second driving unit includes a second pulling-up circuit for selectively coupling the output terminal to the high voltage, a second pulling-down circuit for selectively coupling the output terminal to the low voltage, and a pair of second switches for selectively enabling/disabling the second pulling-up circuit and the second pulling-down circuit. Driving capabilities of the first and second pulling-up circuits are not all equal, and/or driving capabilities of the first and second pulling-down circuits are not all equal.

Interpolator and interpolation cells with non-uniform driving capabilities therein

A method of estimating gain of a time-to-digital converter (TDC) includes: capturing a TDC output sample; calculating a gradient in response to the TDC output sample; and adjusting a TDC normalizing gain based on the calculating step. Another method of calibrating gain of a TDC includes: capturing a phase error which is derived from a TDC output sample, a reference phase and a variable phase; calculating a gradient in response to the phase error; and adjusting a TDC normalizing gain based on the calculating step.

Method and apparatus of estimating/calibrating TDC gain

A time-to-digital system, such as a frequency synthesizer, includes a power management circuit and a time-to-digital converter (TDC). Said power management circuit is coupled to a frequency reference clock and a variable clock, and arranged to output a delayed frequency reference clock and a single pulse of said variable clock ahead of a transition of said delayed frequency reference clock. Said TDC is coupled to said power management circuit and arranged to produce a digital TDC output.

Time-to-digital system and associated frequency synthesizer

A phase/frequency detector for controlling a charge pump includes: a core circuit arranged to output a first phase signal and a second phase signal according to a phase/frequency difference between a reference clock signal and an input clock signal; and a timing circuit coupled to the core circuit and arranged to generate a first control signal and a second control signal for controlling the charge pump according to the first phase signal and the second phase signal, wherein only one of the first control signal and the second control signal is indicative of an enabled operation when the reference clock signal and the input clock signal are substantially identical in phase.

Charge pump, phase frequency detector and charge pump methods

A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter arranged to provide a shifted reference clock by changing phase of a frequency reference clock, and a time-to-digital converter (TDC) for producing a digital TDC output by quantizing a time difference between said RF clock and said shifted reference clock; wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.

Frequency synthesizer and associated method

A method of estimating mismatches of a time-to-digital converter (TDC) includes: capturing phase error samples; calculating difference between the phase error samples and an expected value of the phase error samples; and adjusting correction gain of the TDC based on the calculating step. Another method of estimating mismatches of a TDC includes: capturing TDC output code samples; storing a plurality of accumulation values corresponding to different TDC values respectively, wherein each accumulation value records a number of times a TDC value is carried by the TDC output code samples; calculating a desired value based on the accumulation values; calculating difference between the accumulation values and the desired value; and adjusting correction gain of the TDC based on the calculating step.

Method and apparatus of estimating/calibrating TDC mismatch

A frequency synthesizer includes an oscillator for providing an RF clock, a phase shifter coupled to said oscillator for providing a shifted RF clock by changing phase of said RF clock, and a time-to-digital converter (TDC) coupled to said phase shifter for quantizing a time difference between a frequency reference clock and said shifted RF clock, wherein a range of said TDC covers significantly less than a full range of said RF clock period. An associated method is also provided.

The frequency calibration device includes a logic unit for gating the clock signal according to a gating window signal to generate a gated clock signal, and a divider for dividing the gated clock signal by a divisor in frequency to generate a frequency indication signal, and output digits of the divider are set to the divisor in a calibration cycle, and the frequency indication signal is a most significant bit of the output digits.

Device and method for frequency calibration and phase-locked loop using the same

A charge pump being disposed in a phase locking system. The charge pump includes a sourcing element, a draining element and an offset element. The sourcing element is arranged to selectively source a first current into an output terminal of the charge pump according to a first control signal, and the draining element is arranged to selectively drain a second current from the output terminal according to a second control signal. The offset element is arranged to selectively conduct an offset current via the output terminal according to a third control signal, and one of the sourcing element and the draining element is disabled when the phase locking system is in a phase-locked state.

The present invention applies management frame defined in IEEE 802.11 standard to a wireless distribution system (WDS) mode by adding an information element (IE) into the management frame, which enables any access point (AP) in WDS to maintain IE based on its own setting and state, then send IE via the management frame for providing state of the AP under WDS mode, determine whether a physical link (i.e., a wireless link between APs) should be established therewith based on received IE, and maintain the established physical link through the wireless management frame in a real time manner. Thus, the existence and necessity of the physical link between different APs in WDS can be determined correctly.

Fast and automatic self-forming meshing topology to integrate with wired networks

A reference buffer circuit is disclosed, providing a reference voltage at an output node and comprising a closed-loop branch comprising an amplifier and first and second MOS transistors and an open-loop branch comprising third and fourth MOS transistors and a tracking circuit. The first MOS transistor has a gate coupled to an output terminal of the amplifier and a source coupled to a negative input terminal of the amplifier. The second MOS transistor is coupled to the source of the first MOS transistor. The third MOS transistor has a gate coupled to the output terminal and a source coupled to the output node. The fourth MOS transistor has a drain coupled to the source of the third MOS transistor. A gate voltage of the fourth MOS transistor tracks a drain voltage of the third MOS transistor through the tracking circuit.

Growing community of inventors

Hsinchu County, Taiwan

Yi-Hsien Cho