Pixim, Incorporated

S3 Incorporated, Inc.

Yi-Hen Wei

Ricardo Jansson Motta

David Xiao Dong Yang

William R Bidermann

Odutola Oluseye Ewedemi

Hui Tian

Nalini Ranjan

Zhonghan John Deng

Xi Peng

Henry Yang

Gregg Bardel

David X D Yang

A method of optimizing the exposure times of regions of pixels of an image sensor array during exposure is accomplished by utilizing time interval sampling of an image sensor array comprising of pixels configured to generate digital image signals. Luminance values are extracted from each digital image signal and analyzed to determine if a pixel has reached the optimal exposure. If a pixel has reached the optimal exposure, subsequent digital image signals from this pixel will not be recorded. This preserves the recording of the optimal digital image signal generated by the pixel at the time when the pixel reached its optimal exposure. This process of selectively terminating the recording of digital image signals based on optimal exposures of the pixels can be performed on individual pixels or can be performed on a region of pixels.

Method and apparatus for optimizing exposure time in image acquisitions

Photo-sensors, such as photo-diodes, are formed using regions with cross-sections that increase the overall quantum efficiency of the resulting photo-sensor. The cross-sections have additional (e.g., interior) side-wall interfaces, and, in some embodiments, an additional, relatively shallow bottom interface. The increased total side-wall area and any additional shallow bottom area increase the total photo-junction volume located near the surface of the device. As a result, a greater fraction of photons having relatively small absorption lengths (e.g., blue light) will be absorbed within a photo-junction, thereby increasing the quantum efficiency for those photons. The present invention enables photo-sensors to be implemented with more uniform spectral response.

Photo-sensor cross-section for increased quantum efficiency

Improved conductive pads and conductive lines for use on integrated circuit chips include one or more conductive layers having a wider width than convention conductive lines for improved current and power carrying capacity. A layer of insulating and shock resistant is included over said layers of wider width, and additional pads can be formed on said layer of insulating and shock resistant material. Additional improved conductive pads are formed on the integrated circuit chip over a region containing a conductive line. The improved pads and conductive lines provide high power and current carrying capacity, and simultaneously allow for high pad density on an integrated circuit chip. Said pads and conductive lines can include a layer of metal which is electrically insulated using upper and lower layers of insulating material, with this layer of metal providing shock resistance particularly to such lower layer of insulating material.

High DC current stagger power/ground pad

Growing community of inventors

San Jose, CA, United States of America

Yi-Hen Wei