Spansion Llc.

Advanced Micro Devices Corporation

Infineon Technologies Ag

Infineon Technologies Austria Ag

Maxim Integrated Products, Inc.

Cypress Semiconductor Corporation

Infineon Technologies LLC

Other

Advance Micro Devices, Inc.

Yi He

Zhizheng Liu

Mark W Randolph

Darlene G Hamilton

Wei Zheng

Edward Franklin Runnion

Xuguang Alan Wang

Ming Sang Kwan

Ming-Sang Kwan

Sung-Yong Chung

Xiaowu Gong

Edward Hsia

Sung-Chul Lee

Sameer S Haddad

Meng Ding

Nancy S Leong

Guowei Wang

Zengtao Liu

Tuck Meng Chan

Yugi Mizuguchi

Mark T Ramsbey

Albert M Bergemont

Tazrien Kamal

Shankar Sinha

Ashot Melik-Martirosian

Yong Siang Teo

Jean Yee-Mei Yang

Gulzar Ahmed Kathawala

Kulachet Tanpairoj

Kok Kee Lim

Meng Kiat Jeoh

Yu Nan Sun

Hiroyuki Kinoshita

Timothy J Thurgate

Jean Y Yang

Wei Zhao

Emmanuil Lingunis

Michael A VanBuskirk

Amichai Givant

David Michael Rogers

Xiao Wu Gong

Sheung-Hee Park

Pauling Chen

Mimi Lee

Alykhan Madhani

Mimi Xuefeng Qian

Wing Leung

Gwyn Robert Jones

Sean Lynch

Che-Ping Chen

Kwadwo A Appiah

Winson Siew Teng Wong

Minh Van Ngo

Angela Tai Hui

Richard M Fastow

Lu You

Chi K Chang

Kuo-Tung Chang

Hidehiko Shiraiwa

Pau-Ling Chen

Binh Quang Le

Ning Cheng

Yider Wu

Ming-Huei Shieh

Larry Lingjer Wang

Wenmei Li

Amol Ramesh Joshi

Satoshi Torii

Shivananda Shetty

Hirokazu Tokuno

Yair Sofer

Cinti Xiaohua Chen

Larry Yu Wang

Harry Kuo

Nga-Ching Wong

Yoav Yogev

Michael Brennan

Amir Rochman

Jing Hu

Tio Wei Neo

Siu Kam Kok

Junyang Luo

Bradley Marc Davis

Ihsan Djomehri

Cindy Sun

Eric M Ajimine

Xiang Lu

Ken Tanpairoj

Brian Mooney

Jean Yei-Mei Yang

Phuong Banh

Loi La

Ori Tirosh

Yuji Mizuguchi

Yanxia (Emma) Lin

Xianmin Yi

Yanxiang Liu

Eric Ajimine

Edward Runnion

Emmanuil Manos Lingunis

In an embodiment, a method includes: receiving a first program bit address associated with a plurality of redundant bit addresses and a first transistor-based memory cell, where the plurality of redundant bit addresses are each associated with a respective transistor-based memory cell; providing a programing pulse to a first word line coupled to the first transistor-based memory cell to write a first write value to the first transistor-based memory cell; reading a first bit value from the first transistor-based memory cell; reading redundant bit values from transistor-based memory cells associated with the plurality of redundant bit addresses; when one of the first bit value and the redundant bit values do not match the first write value, determining a majority bit value based on the first bit value and on the redundant bit values; and asserting a flag signal when the majority bit value does not match the first write value.

One-time programmable (ROTP) NVM

Systems, methods, and devices dynamically configure non-volatile memories. Devices include non-volatile memories comprising a plurality of memory regions, each of the plurality of memory regions having a configurable bit density. Devices also include control circuitry configured to retrieve user partition configuration data identifying a plurality of bit densities for the plurality of memory regions, convert a received user address to a plurality of physical addresses based, at least in part, on the plurality of bit densities, compare the user address with the user partition configuration data, and select one of the plurality of physical addresses based, at least in part, on the comparison.

Dynamic configuring of reliability and density of non-volatile memories

A semiconductor device () for improved charge dissipation protection includes a substrate (), a layer of semiconductive or conductive material (), one or more thin film devices () and a charge passage device (). The thin film devices () are connected to the semiconductive or conductive layer () and the charge passage device () is coupled to the thin film devices () and to the substrate () and provides a connection from the thin film devices () to the substrate () to dissipate charge from the semiconductive/conductive layer () to the substrate ().

Method and apparatus for protection against process-induced charging

One embodiment of the present invention relates to a memory cell. The memory cell comprises a substrate and a stacked gate structure disposed on the substrate, wherein the stacked gate structure comprises a charge trapping dielectric layer that is adapted to store at least one bit of data. The memory cell further includes a source and drain in the substrate, wherein the source and drain are disposed at opposite sides of the stacked gate structure. A barrier region is disposed substantially beneath the source or the drain and comprises an inert species. Other embodiments are also disclosed.

Barrier region underlying source/drain regions for dual-bit memory devices

A dynamic trim method includes testing a selected number of cells on a die with predetermined testing margins. Data from this testing is used to determine dynamic reference margins for improving yield. Advantageously, yield is improved by allowing functioning fast or slow units to pass wafer sort by applying the dynamic reference margins for varying processes.

Dynamic trim method for non volatile memory products

Disclosed herein are system, method and computer program product embodiments for utilizing soft programming a nonvolatile memory. An embodiment operates by sequentially applying a single soft programming voltage pulse to all memory cells along each word line in the nonvolatile memory that fail soft programming verification in a first phase. This sequential application of the single soft programming voltage pulse in the first phase may repeat a predetermined number of times or until a threshold is met. Once the predetermined number of times completes, or the threshold is met, soft programming proceeds to a second phase where soft programming remains with each word line until all memory cells along the word line passes soft programming verification.

Multi-pass soft programming

N-channel multi-time programmable memory devices having an N-conductivity type substrate, first and second P-conductivity type wells in the N-conductivity type substrate, N-conductivity type source and drain regions formed in the first P-conductivity type well, the source and drain regions being separated by a channel region, an oxide layer over the N-conductivity type substrate; and a floating gate extending over the channel region and over the second P-conductivity type well in the N-conductivity type substrate, the multi-time programmable memory cell being programmable by hot electron injection and erasable by hot hole injection.

N-channel multi-time programmable memory devices

Dynamic trim method for non-volatile memory products

A system and methodology that can minimize disturbance during an AC operation associated with a memory, such as, program, read and/or erase, is provided. The system pre-charges all or a desired subset of the bit lines in a memory array to a specified voltage, during an AC operation to facilitate reducing AC disturbances between neighboring cells. A pre-charge voltage can be applied to all bit lines in a block in the memory array, or to bit lines associated with a selected memory cell and neighbor memory cells adjacent to the selected memory cell in the block. The system ensures that source and drain voltage levels can be set to desired levels at the same or substantially the same time, while selecting a memory cell. This can facilitate minimizing AC disturbances in the selected memory cell during the AC operation.

Controlling AC disturbance while programming

A system and method for operating power supplies. A method comprises altering a current sense (CS) signal, turning off a switch of the converter in response to a determining that the CS signal is greater than or equal to a first threshold, and leaving on the switch of the converter in response to a determining that the CS signal is less than the first threshold.

System and method for power conversion

An embodiment of the invention relates to an LLC power converter including a controller configured to regulate an output characteristic of the power converter by controlling a power converter switching frequency. In a first mode of operation, the controller turns off a secondary-side power switch earlier than a turn-off time of a primary-side power switch by a time difference that is controlled by a resistor coupled to an external circuit node. In a second mode of operation, the controller turns on a secondary-side power switch at substantially the same time as the primary-side power switch, and turns off the secondary-side power switch after a maximum on time that is a nonlinear function of a load current of the power converter. The nonlinear function is a substantially constant function of the load current for a value of the load current higher than a threshold value.

Controller for a resonant switched-mode power converter

A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Strapping contact for charge protection

An embodiment of the invention relates to a power converter including a resistor divider with an internal node to sense an input line voltage. The internal node is operable as a multifunctional pin. A controller compares a feedback voltage dependent on a power converter output characteristic to a current-sense signal including an offset dependent on a voltage of the internal node to control entry and exit of the power converter from burst mode operation. The node may be employed to manage power converter operation by sensing or controlling its voltage to signal operation in a standby or burst mode, to sense the input line voltage, to enable an external system to signal shutdown to the power converter, and to enable the power converter to signal a delayed restart condition to the external system.

Utilization of a multifunctional pin to control a switched-mode power converter

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Fremont, CA, United States of America

Yi He