Intel Corporation

Yi-Feng Liu

Ramamurthy Krithivas

Bradley A Burres

Balaji Parthasarathy

Pawel Szymanski

Stephan Jourdan

Lily Pao Looi

Sivakumar Radhakrishnan

Bharat S Pillilli

Sin Sim Tan

Phani Kumar Kandula

Jung S Kang

Michael M DeSmith

Suresh Chemudupati

Peter Peide Jeng

Md Monzur Hossain

Generally, this disclosure provides systems, devices, methods and computer readable media for dynamic configuration and enforcement of access lanes to I/O controllers. The System may include a plurality of Input/Output (I/O) controllers and a plurality of lanes. The system may also include a lane mapping module configured to multiplex at least one of the I/O controllers to at least one of the lanes based on a configuration. The system may further include a first processor configured to detect a change request, the change request to modify the configuration from an existing configuration to a new configuration; and a second processor configured to: verify that the new configuration is valid based on a stock keeping unit (SKU) associated with the system; and, if the verification is successful, store the new configuration in non-volatile memory and reset the system.

Dynamic configuration of input/output controller access lanes

An apparatus is provided which includes: a first storage to store one or more parameters, a second storage to store data, and a third storage. The apparatus may further include a first circuitry to detect a triggering event. The apparatus may further include a second circuitry to, in response to the triggering event, cause transfer of the data from the second storage to the third storage, while one or more components of the apparatus is to operate in accordance with the one or more parameters.

Configurable flush of data from volatile memory to non-volatile memory

A method and system to enable power measurements of a system-on-chip in various modes. In one embodiment of the invention, the system-on-chip has full controllability of its logic and circuitry to facilitate configuration of the system-on-chip into a desired mode of operation. This allows hooks or interfaces to access the system-on-chip externally for measurements. For example, in one embodiment of the invention, the hooks in the system-on-chip allow a backend tester to configure the system-on-chip into various modes easily to perform power consumption measurements of one or more individual components of the system-on-chip. The power consumption measurement of the individual components in the system-on-chip can be performed faster and can be more accurate. In addition, the overall yield of the SOC can be increased as it is easier to detect failure parts.

Power measurement techniques of a system-on-chip (SOC)

A plurality of N-doped strip portions are formed alternating with a plurality of P-doped regions. When a voltage is applied to the N-doped strip portions, a capacitance is created between the N-doped strip portions and the P-doped strip portions. A capacitance is also created between the N-doped strip portions and the underlying epitaxial silicon layer. A larger interface area between N-doped and P-doped regions generally increases the capacitance. By providing the N-doped strip portions, as opposed to a continuous N-doped region, the combined interface area between the N-doped strip portions and the underlying epitaxial silicon layer is reduced. However, more interface area is provided between the N-doped strip portions and the P-doped strip portions. A circuit simulation indicates that junction capacitance per unit peripheral length is 0.41 fF/&#x3bc;m, while the junction capacitance per unit area is 0.19 fF/&#x3bc;m^2. Junction capacitance per unit peripheral length thus scales faster than junction capacitance per unit area.

Intrinsic decoupling capacitor

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Chandler, AZ, United States of America

Yi-Feng Liu