Mediatek Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Darwin Precisions Corporation

Yi-Feng Chen

Jiann-Tyng Tzeng

Chih-Liang Chen

Charles Chew-Yuen Young

Kam-Tou Sio

Shang-Chih Hsieh

Chui-Ya Peng

Meng-Hung Shen

Jia-Wei Fang

Yi-Te Chiu

Bo-Jr Huang

Yu-Tung Chang

Heng-Meng Liu

Yu-Jen Lai

Helen Shu-Hui Chang

Chun-Sung Su

Yi-Chun Tsai

Tsung-Ying Tsai

Keng-Kuei Liang

Tung-Kai Tsai

Chih-hung Liu

Yiwei Chen

Shih-Yun Lin

Ya-Shih Huang

Chun-Sheng Huang

Sung-Yun Hsueh

Yan Cing Lin

Chia-Tsun Huang

Hung-Ming Chu

An integrated circuit (IC) may include a plurality of functional blocks, and each functional block of the plurality of functional blocks may include hardware circuits, wherein the plurality of functional blocks may include a first functional block. In addition, the first functional block may include a first macro circuit that is positioned within a first sub-region of the first functional block, wherein among multiple sides of the first sub-region, a first side of the first sub-region is closest to a boundary of the first functional block. Additionally, a first intermediate sub-region of the first functional block is positioned between the first side of the first sub-region and the boundary of the first functional block, and there is no tap cell in the first intermediate sub-region of the first functional block.

Integrated circuit with compact layout arrangement

An electronic switch device and an electronic switch system are provided, wherein the electronic switch system includes: an electronic switch device, which includes: a sensing module, which includes: a pressure sensing module for providing a pressure sensing signal; and a touch control sensing module disposed on the pressure sensing module for providing a touch control sensing signal; and a comparator circuit coupled to the sensing module for receiving the pressure sensing signal.

Electronic switch device and system thereof

A touch indicating cover includes a light-guide plastic piece, a printed circuit layer, an ink layer, a passivation layer, and a light-emitting component. The light-guide plastic piece has a first surface and a second surface opposite to each other, wherein the second surface of the light-guide plastic piece comprises a plurality of microstructures. The printed circuit layer is disposed on the first surface of the light-guide plastic piece. The ink layer is disposed on the printed circuit layer and the first surface of the light-guide plastic piece, wherein the ink layer comprises a light-emitting pattern region corresponding to the microstructures. The passivation film is disposed on the ink layer. The light-emitting component is embedded in the first surface of the light-guide plastic piece and connected to the printed circuit layer, wherein the light-emitting component is disposed adjacent the light-emitting pattern region.

Touch indicating cover and electronic device using the same

An integrated circuit includes a path logic and a timing fixing circuit. The path logic is coupled between an output pin of a first circuit and an input pin of a second circuit. The timing fixing circuit has an input pin coupled to the path logic, and is used to adjust a propagation delay of the path logic. The timing fixing circuit introduces no short-circuit current under normal operation.

Integrated circuit having timing fixing circuit that introduces no short-circuit current under normal operation and associated timing fixing cell in cell library

An apparatus includes a holder configured to carry one or more semiconductor wafers, an arm coupled with the holder, and a detector coupled with either the holder or the arm. The detector is configured to measure a change in weight of the one or more semiconductor wafers. The detector includes a strain gauge weight sensor, a piezoelectric sensor, or any other suitable sensor. The change in weight of the one or more semiconductor wafers is used to determine any possible presence of a broken or missing wafer.

Apparatus and system for detecting wafer damage

The invention provides an inverter. The inverter includes a first converter and a second converter. The first converter is coupled between a supply voltage and an output node of the inverter. The second converter is coupled between the output node of the inverter and a ground voltage. The first converter, the second converter, or both include diode-connected transistors. The propagation delay time of the inverter is substantially a linear function of the temperature of the inverter.

Inverter and ring oscillator with high temperature sensitivity

A clock buffer circuit is provided. The clock buffer circuit receives an input clock signal and generates a delay clock signal. The clock buffer circuit includes an input circuit, an output circuit, a first delay path, and a second delay path. The input circuit receives the input clock signal and generates an output clock signal according to the input clock signal. The output circuit generates the delay clock signal. The first delay path is coupled between the input circuit and the output circuit. The second delay path is coupled between the input circuit and the output circuit. The input circuit selectively provides the output clock signal to a first specific delay path among the first and second delay paths according to a control signal. The output circuit receives the output clock signal which passes through the first specific delay path and outputs the delay clock signal.

Low power clock buffer circuit for integrated circuit with multi-voltage design

A clock gating circuit includes a first transistor, a first inverter and a second transistor. A first terminal of the first transistor receives a clock input signal. A second terminal of the first transistor is coupled to a first node. The first transistor adjusts a voltage of the first node to a first voltage based on the clock input signal. The first inverter is coupled to the first node and receives the voltage of the first node, and outputs a clock output signal. A first terminal of the second transistor receives the clock input signal. A second terminal of the second transistor is coupled to the first node and a second node. The second transistor adjusts the voltage of the first node or the second node to the second voltage, based on the clock input signal.

Clock circuit and method of operating the same

A signal generator includes a main ring oscillator and a first ring oscillator. The main ring oscillator is supplied by a power voltage, and is configured to generate an output oscillation signal. The main ring oscillator is coupled through a power mesh to the power voltage. The first ring oscillator is supplied by the power voltage. The first ring oscillator is similar or identical to the main ring oscillator. The first ring oscillator is coupled through the power mesh to the power voltage. The first ring oscillator is used to calibrate a frequency of the output oscillation signal.

Signal generator and calibrating method thereof

An integrated circuit layout having a mixed track standard cell configuration that having a mixed track standard cell configuration that includes first well regions of a predetermined height and second well regions of a predetermined height, the first and second well regions are arranged within a substrate, first conductors and second conductors arranged and extending across regions of corresponding first and second well regions, and a plurality of standard cells in multiple rows. The standard cells include a first substantially equal to standard cell having a first cell height substantially equal to I(X+Y)+X or Y, wherein X is one half the predetermined height of the first well region, Y is one half the predetermined height of the second well region, and I is a positive integer.

Integrated circuit layout having mixed track standard cell

Growing community of inventors

Xinpu Township, Hsinchu County, Taiwan

Yi-Feng Chen